EDBT 2026 Demo / reviewers in the wild / expert
Run Yan
dblp:331/8056
· DBLP profile ↗
8ranked-venue papers
2as first author
8since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 2 first-author · 8 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A hardware-efficient FPGA-based YOLOv5 accelerator with operator fusion and unified dataflow scheduling
Libo Huang 0002, Run Yan, Lei Wang 0011, Jianzhuang Lu |
Future Gener. Comput. Syst. | 3 |
| 2025 | Brief Announcement: LCTree: A Fast Hardware BVH Constructor for Real-Time Ray TracingabstractUnlike traditional rasterization rendering, ray tracing is a groundbreaking technology that has revolutionized the realistic rendering of images, marking a significant leap forward. However, achieving real-time ray tracing in dynamic scene applications remains a challenging task. This difficulty arises primarily from the substantial technical bottlenecks related to the frequent need for reconstructing or incrementally updating acceleration structures essential for efficient ray calculations. Run Yan, Su Yin, Hui Guo 0004, Yongwen Wang, Gang Chen 0023, Nong Xiao 0001, Libo Huang 0002 |
SPAA | 1 |
| 2025 | Optimizing value prediction for ILP processors: A design space exploration approach
Ling Yang 0008, Libo Huang 0002, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu 0001 |
Integr. | 4 |
| 2024 | QuickTree: A Fast Hardware BVH Construction EngineabstractRay tracing has emerged as a powerful technique for generating visually stunning and realistic images compared to rasterization. With the continuous advancements in computer hardware, modern GPUs have integrated specialized ray tracing acceleration units to enhance rendering capabilities further. However, achieving realtime ray tracing presents a challenge in dynamic scenes, where spatial data structures used for accelerated rendering must be reconstructed or updated when there are changes in the scene primitives. This paper introduces QuickTree, a novel Bounding Volume Hierarchy (BVH) construction engine based on the linear BVH (LBVH) optimization algorithm. QuickTree addresses the challenge of dynamic scenes support by employing a highly parallel and pipelined system design. This innovative approach ensures fast construction speed. QuickTree demonstrates significant performance improvements. Compared to the currently fastest MergeTree, it has increased construction speed by 10% and reduced area by 45% compared to RayCore, which has the smallest chip area. Yin Su, Hui Guo 0004, Run Yan, Yongwen Wang, Nong Xiao 0001, Gang Chen 0023, Libo Huang 0002 |
CF | 3 |
| 2024 | Cost-Effective Value Predictor for ILP processors through Design Space ExplorationabstractValue prediction is a microarchitectural technique that enhances processor performance by speculatively breaking true data dependencies. It has demonstrated improved performance in both single-threaded and multi-threaded workloads, rendering it an appealing microarchitectural approach. While high-performance value predictors can achieve impressive accuracy, they may also incur significant costs in terms of area, power consumption, and complexity. Therefore, there is a demand for lightweight value prediction techniques capable of striking a favorable balance between performance and overhead. However, designing value predictors with superior performance using limited resources presents an urgent challenge. Consequently, this work proposes a design space exploration framework for the state-of-the-art EVES value predictor, aiming to efficiently configure the design parameters of the value predictor within constrained RAM resources. Additionally, the article evaluates the performance of the explored value predictor across a wide range of workloads. The explored value predictors exhibit high efficiency across RAM sizes ranging from 2KB to 16KB while maintaining acceptable computational complexity. Furthermore, the results indicate that the explored value predictor achieves optimal efficiency under the 2KB constraint, with the highest acceleration-to-cost ratio reaching 4.02%/KB. Ling Yang 0008, Libo Huang 0002, Run Yan, Sheng Ma, Yongwen Wang, Weixia Xu 0001 |
ACM Great Lakes Symposium on VLSI | 4 |
| 2024 | MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray TracingabstractRay tracing has been regarded as the future of graphics rendering technology for a long time. However, interactive ray tracing still faces challenges, especially in mobile devices, such as high computational intensity and multiple branches. In this brief, we aim to maximize overall efficiency by leveraging all forms of potential parallelism, including task, basic block, loop, and pipeline levels. We present multilevel parallel ray tracing accelerator (MPRTA), an innovative mobile accelerator that offers high performance and optimal efficiency for ray tracing. Experimental results indicate that MPRTA is$1.67\times $more efficient than the currently best-reported mobile accelerator. Run Yan, Yin Su, Hui Guo 0004, Yashuai Lü, Nong Xiao 0001, Li Shen 0007, Yongwen Wang, Libo Huang 0002 |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2022 | Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications
Hongbing Tan, Run Yan, Ling Yang 0008, Libo Huang 0002, Liquan Xiao, Qianming Yang |
ICA3PP | 2 |
| 2022 | Optimizing Winograd Convolution on GPUs via Partial Kernel Fusion
Gan Tong, Run Yan, Ling Yang 0008, Mengqiao Lan, Yuanhu Cheng, Yashuai Lü, Sheng Ma, Libo Huang 0002 |
NPC | 2 |