EDBT 2026 Demo / reviewers in the wild / expert
Abhinandan Pal
dblp:331/8328
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2025
0000-0002-4122-5092ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Automated reasoning and model checking · 66% Logic in computer science · 34% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Automated reasoning and model checking › program verification
inductive invariants |
0.9 | 1 | 2025 | Let a Neural Network be Your Invariant · NeurIPS 2025 |
Automated reasoning and model checking › temporal logic verification
liveness verification |
0.9 | 1 | 2025 | Let a Neural Network be Your Invariant · NeurIPS 2025 |
Logic in computer science › program analysis
ranking functions |
0.9 | 1 | 2025 | Let a Neural Network be Your Invariant · NeurIPS 2025 |
Electronic design automation › hardware verification and test
formal verification |
0.8 | 1 | 2024 | Neural Model Checking · NeurIPS 2024 |
Electronic design automation › hardware verification and test
hardware verification |
0.8 | 1 | 2024 | Neural Model Checking · NeurIPS 2024 |
Automated reasoning and model checking › model checking
temporal logic model checking |
0.8 | 1 | 2024 | Neural Model Checking · NeurIPS 2024 |
Logic in computer science › temporal logic › linear temporal logic
LTL specifications |
0.3 | 1 | 2025 | Let a Neural Network be Your Invariant · NeurIPS 2025 |
Logic in computer science
temporal logic |
0.3 | 1 | 2025 | Let a Neural Network be Your Invariant · NeurIPS 2025 |
Automated reasoning and model checking
satisfiability |
0.2 | 1 | 2024 | Neural Model Checking · NeurIPS 2024 |
Methods — techniques the papers use, named apart from their topics
unsupervised learning · 1.5satisfiability solving · 1.5neural networks as proof certificates · 1.5neural certificate architecture · 0.9gradient descent · 0.9constraint solver training · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Let a Neural Network be Your InvariantabstractSafety verification ensures that a system avoids undesired behaviour.
Liveness complements safety, ensuring that the system also achieves its
desired objectives. A complete specification of functional correctness must
combine both safety and liveness. Proving with mathematical
certainty that a system satisfies a safety property demands presenting an
appropriate inductive invariant of the system, whereas proving liveness
requires showing a measure of progress witnessed by a ranking function.
Neural model checking has recently introduced a data-driven approach to the
formal verification of reactive systems, albeit focusing on ranking
functions and thus addressing liveness properties only. In this paper, we
extend and generalise neural model checking to additionally encompass
inductive invariants and thus safety properties as well. Given a system and
a linear temporal logic specification of safety and liveness, our approach
alternates a learning and a checking component towards the construction of a
provably sound neural certificate. Our new method introduces a neural
certificate architecture that jointly represents inductive invariants as
proofs of safety, and ranking functions as proofs of liveness. Moreover,
our new architecture is amenable to training using constraint solvers,
accelerating prior neural model checking work otherwise based on gradient
descent. We experimentally demonstrate that our method is orders of
magnitude faster than the state-of-the-art model checkers on pure liveness
and combined safety and liveness verification tasks written in
SystemVerilog, while enabling the verification of richer properties than was
previously possible for neural model checking. Mirco Giacobbe, Daniel Kroening, Abhinandan Pal, Michael Tautschnig |
NeurIPS | 3 |
| 2024 | Neural Model CheckingabstractWe introduce a machine learning approach to model checking temporal logic, with application to formal hardware verification. Model checking answers the question of whether every execution of a given system satisfies a desired temporal logic specification. Unlike testing, model checking provides formal guarantees. Its application is expected standard in silicon design and the EDA industry has invested decades into the development of performant symbolic model checking algorithms. Our new approach combines machine learning and symbolic reasoning by using neural networks as formal proof certificates for linear temporal logic. We train our neural certificates from randomly generated executions of the system and we then symbolically check their validity using satisfiability solving which, upon the affirmative answer, establishes that the system provably satisfies the specification. We leverage the expressive power of neural networks to represent proof certificates as well as the fact that checking a certificate is much simpler than finding one. As a result, our machine learning procedure for model checking is entirely unsupervised, formally sound, and practically effective. We experimentally demonstrate that our method outperforms the state-of-the-art academic and commercial model checkers on a set of standard hardware designs written in SystemVerilog. Mirco Giacobbe, Daniel Kroening, Abhinandan Pal, Michael Tautschnig |
NeurIPS | 3 |
| 2024 | Abstract Interpretation-Based Feature Importance for Support Vector Machines
Abhinandan Pal, Francesco Ranzato, Caterina Urban, Marco Zanella |
VMCAI (1) | 1 |