Gate sizing is a critical step in achieving the target power, performance, and area (PPA) in chip design. In recent years, machine learning (ML) methods have recently emerged as a new paradigm for gate sizing. Their promising results have gained attention; however, the practical applicability and performance of existing works is limited by at least one of the following factors: (1) long runtime due to test-time optimization or autoregressive prediction; (2) limited exploration of architectural choices; (3) an overly simplified data representation, known as a homogeneous graph, which merges pins and cells into a single node. To improve both practicality and performance, we introduce a novel MLbased gate sizer, dubbed DPH-Sizer, which directly predicts the appropriate gate sizes using a heterogeneous graph that separates cells and their pins into distinct nodes. This heterogeneous graph explicitly captures the relationships between different circuit elements, leading to enhanced performance. Lastly, we propose InterCell and Intra-Cell GAT blocks to explicitly capture both intracell and inter-cell information. These are followed by transformer blocks, which are placed at the end of the GAT stack to capture global path-level features. In our experiments, we validate each of the proposed components and demonstrate that DPH-Sizer maintains power consumption within 2.0% on average while achieving improvements of 54.3% in timing (WNS) and 1.3% in area metrics.

As technology nodes advance and feature sizes shrink, the increasing complexity of design rules and routing congestion has resulted in greater design challenges and rising costs. Machine learning (ML) models offer significant potential to enhance design quality by enabling early prediction and optimization during the design flow. However, only a few works have validated the effectiveness of ML model when integrated to the traditional design flow. This paper will cover the effectiveness of ML-enhanced design workflow with some practical applications. Additionally, we will address which problems should be solved to achieve successful ML integration.

Large language models (LLMs) have recently attracted significant attention for their potential in Verilog code generation. However, existing LLM-based methods face several challenges, including data scarcity and the high computational cost of generating prompts for fine-tuning. Motivated by these challenges, we explore methods to augment training datasets, develop more efficient and effective prompts for fine-tuning, and implement training methods incorporating electronic design automation (EDA) tools. Our proposed framework for fine-tuning LLMs for Verilog code generation includes (1) abstract syntax tree (AST)-based data augmentation, (2) output-relevant code masking, a prompt generation method based on the logical structure of Verilog code, and (3) reinforcement learning with tool feedback (RLTF), a fine-tuning method using EDA tool results. Experimental studies confirm that our framework significantly improves syntax and functional correctness, outperforming commercial and non-commercial models on open-source benchmarks.

We introduce RL-Fill, a novel reinforcement learning framework for timing-aware fill insertion. RL-Fill first generates a large number of fills in the empty spaces and then removes the timing-critical fills as determined by the policy network. Towards faster convergence and stability, our framework employs a two-phase training process. In the first phase, we train the policy with offline expert data using an imitation learning scheme. In the second phase, we further optimize the policy with online data using reinforcement learning. Moreover, we propose a new data augmentation method, LayoutMix, to ensure data-efficient training despite limited number of expert data. Our results demonstrate that RL-Fill is competitive to the commercial tool and outperforms the previous machine learning-based method in timing metrics while adhering density constraints.