Single Flux Quantum (SFQ) digital logic offers a promising path to energy-efficient, high-performance computing, but faces significant scalability challenges–particularly due to the area overhead associated with gate-level path balancing and the pipelining of splitter trees. Prior efforts to reduce this overhead often unnecessarily compromise throughput, diminishing SFQ’s key performance advantage. To mitigate this, we propose a timing-aware optimization framework that unifies and enhances both traditional full path balancing (FPB) and multi-phase clocking approaches. Inspired by timing-driven EDA strategies in CMOS, our approach explicitly models gate delays and jointly optimizes clock phase assignments, pipelining, and splitter tree construction, minimizing area and latency overhead while achieving a given performance target. On benchmark circuits, our timing-aware 2-phase clocking achieves up to 30% area and 29% latency reductions over FPB at a 27ps clock period. Compared to prior multi-phase methods operating at 42ps, we achieve 22% lower area and 23% lower latency. At a tighter 21ps performance target, our timing-aware single-phase clocking improves area and latency by 28% and 7%, respectively. All optimizations are implemented using scalable, polynomial-time algorithms.

Positioned as a highly promising post-CMOS computing technology, superconductor electronics (SCE) offer the potential for unparalleled performance and energy efficiency gains compared to end-of-roadmap CMOS circuits. However, achieving very large-scale integration poses numerous challenges. These challenges span from the modeling and analysis of superconducting devices and logic gates to the intricate design of complex SCE circuits and systems. Addressing power and clock distribution issues, minimizing adverse effects of flux trappings, and mitigating stray electromagnetic fields in sensitive SCE circuitry are key challenges that need attention. Verification and testing of SCE circuits also remain open problems. Moreover, scaling the minimum feature sizes of SCE circuits, currently set at 150nm, presents critical scaling and physical design challenges that must be overcome. This review aims to delve into these issues, providing detailed insights while exploring existing or potential solutions to overcome them.

Spiking Neural Networks (SNNs) have emerged as an attractive spatio-temporal computing paradigm for complex vision tasks. However, most existing works yield models that require many time steps and do not leverage the inherent temporal dynamics of spiking neural networks, even for sequential tasks. Motivated by this observation, we propose an optimized spiking long short-term memory networks (LSTM) training framework that involves a novel ANN-to-SNN conversion framework, followed by SNN fine-tuning via backpropagation through time (BPTT). In particular, we propose novel activation functions in the source LSTM architecture and convert a judiciously selected subset of them to leaky-integrate-and-fire (LIF) activations with optimal bias shifts. Moreover, we propose a pipelined parallel processing scheme that hides the SNN time steps, significantly improving system latency, especially for long sequences. The resulting SNNs have high activation sparsity and require only accumulate operations (AC), in contrast to expensive multiply-and-accumulates (MAC) needed for ANNs, except for the input layer when using direct encoding, yielding significant improvements in energy efficiency. We evaluate our framework on sequential learning tasks including temporal MNIST, Google Speech Commands (GSC), and UCI Smartphone datasets on different LSTM architectures. We obtain test accuracy of 94.75 % with only 2 time steps on the GSC dataset with$\sim 4.1\times$lower energy than an iso-architecture standard LSTM.