The conventional capacitor-switch-inductor (C-S-L) topology suffers from significant conduction loss and sluggish transient response due to the series power switches conduction inherent in its structure. To address these limitations, the proposed rotated hybrid converter adopts a rotated mechanism and parallel conduction within the capacitor-two-switch-inductor (C-2S-L) topology, effectively reducing current stress on components. This approach enhances efficiency while mitigating the effects of parasitic inductance from bond wires. During transient conditions, all C-2S-L stages can be simultaneously activated, enabling a near-full duty cycle (D). Experimental results demonstrate a minimal undershoot of 96 mV and a fast settling time of 0.92 μs during a load step from 2 A to 10 A within 20 ns. Additionally, the converter integrates phase shedding, dynamically adjusting the number of active phases according to load conditions to optimize efficiency across a broad load range. Therefore, the proposed C-2S-L topology achieves a peak efficiency of 92.6% at an output voltage (VOUT) of 1.2 V and a load current (ILOAD) of 3A.

This paper proposes an isolated gate driver that incorporates an enhanced common-mode transient immunity (CMTI) technique to effectively suppress common-mode transient (CMT) noise. Additionally, the approach leverages the CMT noise to enable on-the-fly deadtime (DT) control at the transmitter. Experimental results demonstrate the DT jitter compensation circuit reduces high-frequency carrier (500 MHz) jitter by 10.6%, the efficiency is improved by 11.5%, and the CMTI is improved from 184 kV/μs to 208 kV/μs.

this paper proposes a new dual-mode low-dropout linear regulator without external capacitors, which includes three error amplifiers, an offset voltage generator, a mode decision circuit, and a pre-biasing load transient enhancement circuit. The chip uses a 28nm CMOS process to verify the advantages brought by the architecture of this work. The measurement results show that the output voltage has a negligible undershoot and overshoot (both less than 5mV) during mode transition. In load transient response, due to the use of pre-charge technique, the output voltage undershoot and overshoot are reduced by 45.2% and 36%, respectively. Finally, this architecture achieves FoM to be close to 1fs.

the proposed distributive digital low dropout (DLDO) regulator utilizes the triple binary successive approximation recursive (SAR) control algorithm for fast transient response. In addition, the body voltage control (BVC) can be used to expand the least significant bit (LSB) to enhance the accuracy. In case of load transients, the BVC can further increase or decrease the driving capability for fast transient response. Experimental results show that the voltage droop can be less than 72 mV at $F_{\text{CLK}}=100 \text{MHz}$, accomplishing a fast settling time of 3.6 ns. Burst cells and lossless cells can maintain overshoot below 68 mV with the settling time of 11.2 ns. The BVC technique reduces output voltage ripple to less than 0.4 mV in the steady-state.