Design Space Exploration (DSE) is essential for tuning CPU microarchitectural parameters to achieve favorable trade-offs among performance, power, and area. Prior efforts have mainly focused on improving search algorithms to find better design points; however, the growing complexity of modern processors has made design evaluation increasingly time consuming, with simulation costs becoming the dominant bottleneck that limits the efficiency of DSE. To address this challenge, we present FastDSE, an open-source FPGA accelerated DSE framework. FastDSE offloads RTL simulation to the FPGA and executes the DSE search algorithm on the host. To support rapid evaluation of different design points, it decouples logical microarchitectural parameters from physical hardware resources with minor RTL modifications, enabling runtime CPU parameter reconfiguration without FPGA re-synthesis. To support diverse DSE search algorithms and processor designs, FastDSE provides lightweight APIs for host-FPGA interaction and simulation metrics collection. Evaluated on an out-of-order RISC-V processor and representative algorithms, FastDSE reduces simulation time by 99.87%, boosts exploration throughput by up to 68.7 ×, and delivers up to 30.7% PPA improvement over the baseline.

•Overview •Microarchitecture design •Agile development platform •Applications in industry & academia •Summary

TileLink is a standard interface used for on-chip communication within the RISC-V open-source processor ecosystem. It offers a scalable, low-latency, and coherent method of exchanging data between various components of a System-on-Chip (SoC) design, such as processors, accelerators, and memory controllers. Certain components within the SoC may include caches, and TileLink Cached(TL-C) coherence protocols are implemented to ensure cache coherence among these components. The TL-C protocols are hierarchical and can be configured to operate in either inclusive or non-inclusive modes. Due to the complexity and difficulty of these protocols, our investigation focuses on utilizing model checking techniques. In this paper, we present a novel approach to construct a simple and flexible cache hierarchy in the model checking tool Murphi. We verified the generic formal models that adhere to the recent TL-C specifications proposed by SiFive with inclusive or non-inclusive policies for the first time. In particular, we have examined the shapes of cache coherence trees and their generation within the aforementioned inclusion policies.

While research has shown that the agile chip design methodology is promising to sustain the scaling of computing performance in a more efficient way, it is still of limited usage in actual applications due to two major obstacles: 1) Lack of tool-chain and developing framework supporting agile chip design, especially for large-scale modern processors. 2) The conventional verification methods are less agile and become a major bottleneck of the entire process. To tackle both issues, we propose MINJIE, an open-source platform supporting agile processor development flow. MINJIE integrates a broad set of tools for logic design, functional verification, performance modelling, pre-silicon validation and debugging for better development efficiency of state-of-the-art processor designs. We demonstrate the usage and effectiveness of MINJIE by building two generations of an open-source superscalar out-of-order RISC-V processor code-named XIANGSHAN using agile methodologies. We quantify the performance of XIANGSHAN using SPEC CPU2006 benchmarks and demonstrate that XIANGSHAN achieves industry-competitive performance.