Demo Data from EDBT 2026 / reviewers in the wild / expert
Andrea Fanti 0002
dblp:332/4322-2
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2022
0000-0002-8881-6658ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Systems and software security · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Systems and software security
memory safety |
0.6 | 1 | 2022 | Toward Register Spilling Security Using LLVM and ARM Pointer Authentication · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Systems and software security › memory protection
pointer authentication |
0.6 | 1 | 2022 | Toward Register Spilling Security Using LLVM and ARM Pointer Authentication · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Systems and software security › trusted computing
trusted execution |
0.6 | 1 | 2022 | Toward Register Spilling Security Using LLVM and ARM Pointer Authentication · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
LLVM compiler passes · 1.1ARM pointer authentication · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Toward Register Spilling Security Using LLVM and ARM Pointer AuthenticationabstractModern reduced instruction set computer processors are based on a load/store architecture, where all computations are performed on register operands. Compilers therefore allocate registers based on demand, and when occupancy is at maximum, register contents are spilled onto the stack and then retrieved later as data is needed. This phenomenon has security implications that cannot be ignored, as data on the stack is subject to well-known memory corruption attacks. Moreover, works presented so far are mainly targeting protection of pointers to code (e.g., return addresses), but are ineffective for protecting other context data in the stack. This article presents a security solution for spilled registers, generalizing the use of ARM pointer authentication (PA) for this purpose. The protection is enforced by the LLVM compiler via additional compiler passes and modifications. The solution provides guarantees for both integrity and confidentiality protection, and also addressing reuse attack problems associated with PA usage. Experimental data collected demonstrates the effectiveness of the solution against corruption and eavesdropping. We test our solution using SPEC CPU 2017, which confirms the functional viability of our solution. Additionally, we expose real-world performance overhead metrics of our protection design on a ARM-PA-enabled processor. Andrea Fanti 0002, Carlos Chinea Perez, Rémi Denis-Courmont, Gianluca Roascio, Jan-Erik Ekberg |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |