EDBT 2026 Demo / reviewers in the wild / expert
Yin-Chiuan Chen
dblp:332/4450
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2022
0000-0001-6283-1297ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 75% Compilers and program optimization · 25% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 50% Storage systems · 50% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Operating systems › resource management
memory management |
0.6 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Operating systems › resource management › memory management › virtual memory
page fault handling |
0.6 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Compilers and program optimization
prefetching |
0.6 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Operating systems › resource management › memory management
virtual memory |
0.6 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Memory systems
non-volatile memory |
0.2 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Storage systems › storage performance
ultra-low-latency storage |
0.2 | 1 | 2022 | Exploring Synchronous Page Fault Handling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
adaptive CPU scheduling · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Exploring Synchronous Page Fault HandlingabstractThe advance of nonvolatile memory in storage technology has presented challenges in redefining the ways in handling the main memory and the storage. This work is motivated by the strong demands in effective handling of page faults over ultralow-latency storage devices. In particular, we propose synchronous and asynchronous prefetching strategies to satisfy process executions with different memory demands in supporting of synchronous page fault handling. An adaptive CPU scheduling strategy is also proposed to cope with the needs of processes in maintaining their working sets in the main memory. Six representative benchmarks and applications were evaluated. It was shown that our strategy can effectively save 12.33% of the total execution time and reduce 13.33% of page faults, compared to the conventional demand paging strategy with nearly no sacrificing of process fairness. Yin-Chiuan Chen, Chun-Feng Wu, Yuan-Hao Chang 0001, Tei-Wei Kuo |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |