Eigenpair computation is fundamental in machine learning and signal processing but faces$\mathbf {O(n^{3})}$complexity and data movement limits on digital platforms. Resistive random-access memory (RRAM)-based analog matrix computing (AMC) offers a low-latency, in-memory alternative, enabling$\mathbf {O(1)}$matrix operations by encoding matrices as conductance and exploiting circuit laws. Previous AMC eigenvector circuit can compute the dominant eigenvector but requires prior knowledge of the corresponding eigenvalue, and is incapable of solving for all eigenpairs. This work introduces an approach that decomposes eigenpair computation into matrix inversion task and eigenvalue determination by sweeping, enabling two RRAM-based AMC circuit designs: the modified-INV circuit for dominant eigenpair computation and the modified-GINV circuit for all eigenpairs computation. Applied to principal component analysis, the modified-GINV circuit generated principal components for the Iris dataset and extracted eigenfaces for image reconstruction —both closely matching the theoretical values. Moreover, we investigated the impact of non-ideal factors, including RRAM device variation, operational amplifier input offset voltage, and interconnect resistance, as well as power consumption, providing valuable guidance for evaluating circuit performance.

In-memory analog matrix computing (AMC) with resistive random-access memory (RRAM) represents a highly promising solution that solves matrix problems in one step. However, the existing AMC circuits each have a specific connection topology to implement a single computing function, lack of the universality as a matrix processor. In this work, we design a reconfigurable AMC macro for general-purpose matrix computations, which is achieved by configuring proper connections between memory array and amplifier circuits. Based on this macro, we develop a hybrid system that incorporates an on-chip write-verify scheme and digital functional modules, to deliver a general-purpose AMC solver for various applications.

Recently, in-memory analog matrix computing (AMC) with nonvolatile resistive memory has been developed for solving matrix problems in one step, e.g., matrix inversion of solving linear systems. However, the analog nature sets up a barrier to the scalability of AMC, due to the limits on the manufacturability and yield of resistive memory arrays, non-idealities of device and circuit, and cost of hardware implementations. Aiming to deliver a scalable AMC approach for solving linear systems, this work presents BlockAMC, which partitions a large original matrix into smaller ones on different memory arrays. A macro is designed to perform matrix inversion and matrix-vector multiplication with the block matrices, obtaining the partial solutions to recover the original solution. The size of block matrices can be exponentially reduced by performing multiple stages of divide-and-conquer, resulting in a two-stage solver design that enhances the scalability of this approach. BlockAMC is also advantageous in alleviating the accuracy issue of AMC, especially in the presence of device and circuit non-idealities, such as conductance variations and interconnect resistances. Compared to a single AMC circuit solving the same problem, BlockAMC improves the area and energy efficiency by 48.83% and 40%, respectively.

Analog matrix computing (AMC) with resistive memory implies naturally massive parallelism and in-memory processing, thus representing a promising solution for accelerating data-intensive workloads in many applications. In AMC circuits, the interconnect resistances residing in the crosspoint resistive arrays arise as a main non-ideal factor degrading the computing accuracy. Simulating and optimizing the circuits are of fundamental importance for large system integration. In this work, we develop a physics-based iterative algorithm to quickly model the matrix-vector multiplication (MVM) operation of crosspoint resistive array with interconnect resistances, thus quadratically reducing the time complexity of circuit simulation. In addition, we propose a new MVM circuit for matrix with negative values, in parallel with the conventional column-wise splitting (CS) and row-wise splitting (RS) circuits. The circuit is based on the conductance compensation (CC) strategy to realize a simplified RS scheme. The discrete Fourier transform (DFT) is implemented using this circuit as a case study. Simulation results reveal that the computing error caused by interconnect resistances is remarkably reduced in the CC-RS circuit. Also, the CC-RS scheme is demonstrated to be more immune to device variations and source/sink resistances. Our results provide an efficient modeling method together with an optimized approach for AMC circuits with non-idealities.