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Jungsub Rhim

dblp:332/5331 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Efficient and distributed learning · 56% Deep learning architectures and training · 44%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning › automated machine learning
architecture search efficiency
0.612022
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Machine learning › Deep learning architectures and training › convolutional neural network
convolutional neural network architecture
0.612022
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Hardware accelerators and domain-specific architectures › neural architecture search
hardware-aware neural architecture search
0.612022
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Hardware accelerators and domain-specific architectures
neural architecture search
0.612022
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Machine learning › Efficient and distributed learning
model compression
0.212022
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022

Methods — techniques the papers use, named apart from their topics

differential architecture search · 1.1compound scaling · 1.1Single-Path NAS · 1.1
YearPublicationVenuePosition
2022 SNAS: Fast Hardware-Aware Neural Architecture Search Methodology
abstract
Recently, automated neural architecture search (NAS) emerges as the default technique to find a state-of-the-art (SOTA) convolutional neural network (CNN) architecture with higher accuracy than manually designed architectures for image classification. In this article, we present a fast hardware-aware NAS methodology, called S3NAS, reflecting the latest research results. It consists of three steps: 1) supernet design; 2) Single-Path NAS for fast architecture exploration; and 3) scaling and post-processing. In the first step, we design a supernet, superset of candidate networks with two features: one is to allow stages to have a different number of blocks, and the other is to enable blocks to have parallel layers of different kernel sizes (MixConv). Next, we perform a differential search by extending the Single-Path NAS technique to support the MixConv layer and to add a latency-aware loss term to reduce the hyperparameter search overhead. Finally, we use compound scaling to scale up the network maximally within the latency constraint. In addition, we add squeeze-and-excitation (SE) blocks and h-swish activation functions if beneficial in the post-processing step. Experiments with the proposed methodology on four different hardware platforms demonstrate the effectiveness of the proposed methodology. It is capable of finding networks with better latency–accuracy tradeoff than SOTA networks, and the network search can be done within 4 h using TPUv3.
Jaeseong Lee 0002, Jungsub Rhim, Duseok Kang, Soonhoi Ha
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2