Test scheduling is a process that manages tests within a System-on-Chip (SoC) to minimize test time by allocating test resources and adjusting priorities. Efficient test scheduling offers cost saving opportunities by reducing test time without compromising test coverage. Since test scheduling is a NP-hard problem, conventional methods adopt optimization or heuristic algorithms that leverage metrics of each test. However, due to the interdependence of tests based on how limited resources are allocated, finding the optimal solution to minimize test time is challenging. In this article, a dynamic pairing algorithm is proposed to consider the mutual influence of tests on each other in the test scheduling process. The proposed method identifies the available test resources for a specific pair and minimizes the test time of the paired modules under identified constraints. Additionally, the proposed algorithm employs a heuristic-based approach to test scheduling to reduce the CPU time needed for scheduling. The proposed heuristic algorithm sequentially schedules test target modules and determines the optimal test schedule through dynamic pairing. Experiments have been carried out on diverse benchmarks and under various constraint conditions. The results indicate that the proposed method achieves shorter test times on average in comparison to conventional methods.

Logic diagnosis is essential for improving reliability and yield. In conventional diagnosis methods, although various methods are proposed to enhance the accuracy and resolution of logic diagnosis, there are still diagnosis results where the reported locations of defects are incorrect. Particularly in logic circuits, which contain a large number of gates, multiple faults can occur, not just single faults. Since the number of possible cases for multiple faults is significantly greater compared to single faults, the diagnosis of multiple faults is complicated. To address this problem, a new diagnosis method that uses a multistage process with fault candidate reduction is proposed. In the proposed method, machine learning is used with fault candidate reduction, and post-processing is performed after the use of machine learning. This proposed method allows for the analysis of multiple faults using only the test responses for single faults, demonstrating that this method can maintain sufficient accuracy and resolution for unexpected faults.

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.