Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize$w$=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively.

As an extension of traditional CNNs, three dimensional convolutional neural networks (3D CNNs) impose significantly higher computational and storage demands compared to their two-dimensional counterparts (2D CNNs). This has led to increased interest in exploring FPGA hardware acceleration methods for 3D CNNs. The R(2+l)D model significantly improves performance compared to conventional 3D CNN architectures. However, due to its incorporation of multiple convolution kernel types and shortcut connections, its hardware design complexity surpasses that of traditional 3D CNNs. This paper presents an efficient computing architecture for (2+l)D convolutions and an FPGA acceleration system for R(2+1)D models. Through systematic exploration of the design space and aligning architectural strategies with FPGA device layout characteristics, a balanced trade-off between parallelism and resource utilization is achieved within the acceleration system. Performance evaluation conducted on the Alveo U50 platform reveals that the accelerator achieves a throughput of 1511 GOP/s. Compared to the Ryzen 3960X CPU, our design exhibits an 8.8× throughput enhancement and a significant 83.5% reduction in latency. Similarly, compared to the RTX 3090 GPU, our design achieves an impressive 12.3×improvement in power efficiency. In contrast to the latest FPGA hardware acceleration design for the R(2+l)D model, our design not only achieves higher throughput but also delivers a 4.7× enhancement in DSP efficiency. When compared to hardware accelerators designed for C3D models, our design demonstrates a roughly equivalent throughput.