Many combinatorial optimization problems map naturally to Ising Hamiltonians, $H({\text{s}}) = - \sum\nolimits_{i,j} {{J_{ij}}} {s_i}{s_j} - \sum\nolimits_i {{h_i}} {s_i}$ , and CMOS ring-oscillator Ising machines solve them in microseconds at milliwatts [1] , [2] . Their key limitation is capacity : the number of spins one solver core can process in a single solve. Because each hardware spin represents one binary Ising variable, capacity directly sets the largest problem solvable in one shot. Our 28 nm five-core COBI chip solves a 45-spin all-to-all subproblem per core in 77.5 µ s, so larger instances require iterative decomposition. This shifts the bottleneck from analog solving to digital orchestration: a CPU-based decomposer needs ∼321 µ s/iter over PCIe, 4× the core solve time, leaving the solver idle 84.9% of the time. We instead co-locate an FPGA decomposer with the chip and derive sizing laws for the required parallelism, achieving 1.93× geomean speedup and > 40× energy reduction vs. an optimized C++ baseline.

Model-Based Diagnosis (MBD) identifies faulty components in complex systems by reasoning over a model of expected behavior and observations. Computing minimal-cardinality diagnoses—those involving the smallest number of faulty components—is NP-hard and becomes challenging for large systems due to the combinatorial growth of possible fault combinations. SAT-based formulations provide a compact representation of diagnostic constraints, allowing the diagnosis problem to be expressed as a combinatorial optimization problem. Since Ising Machines are well suited for solving such problems, this representation offers a natural pathway for mapping MBD to Ising-based computation. In this work, we present MIBID, a framework that maps SAT-based MBD formulations to an Ising model for computing minimal-cardinality diagnoses. The framework also incorporates hardware-aware pre-processing and decomposition to adapt the formulation to the capabilities of an Ising Machine. Experimental results on a manufactured Ising Machine show competitive performance with SAT-based methods for single minimal diagnoses. For multiple-diagnosis tasks, MIBID enumerates up to \(34\%\) and \(43.59\%\) more diagnoses than state-of-the-art under the weak and strong fault models, respectively, thereby providing broader coverage of plausible fault explanations.

In complex processor micro-architectures with multi-cores, multiple-issue, out-of-order execution schemes, etc., it is crucial to be able to trace the program flow to design a processor hardware and software as bug-free as possible for reliability, safety and mission critical systems. Therefore, the trace-ability of a program’s execution flow is significant during processor hardware and software development cycles. In this paper, we present a hardware design and implementation of a Trace Encoder Intellectual Property (IP) that supports the multiple instructions retirement on RISC-V processor cores. Implementation follows the Efficient Trace for RISC-V processor non-Instruction Set Architecture (non-ISA) specification [1]. Moreover, a novel algorithm is introduced that is capable of capturing both single and multiple retirement of micro-operations in a multiple-issue processor core, and feeding the Trace Encoder IP with the correct micro-operation sequence through the ingress port. Results show encoding ratios down to 2.11 bits/instruction. The Trace Encoder IP has a low area overhead of 3.74%, and only consumes 3.41% of the total power w.r.t. the processor core in a commercial 28 nm CMOS process.