This paper analyses the phase performance of a RX front-end architecture implemented in a 65-nm CMOS process for linear phased arrays at 24 GHz. The front-end is based on an array of LNAs and phase shifters, which can be used in analog and hybrid beamformers. The penalties of the radiation pattern are associated with metrics calculated from the phase performance. PVT variations and mismatch have been included. Results show that the front-end could potentially attain, in spite of PVT variations, a value near the defined by the mismatch.

This paper presents the design of a differential quadrature all-pass filter as a quadrature generator for being used in a phase shifter operating at 19.5 GHz, employing 65 nm CMOS technology. Various solutions have been investigated to address errors occurring in the phase and magnitude of I/Q signals at the output of the quadrature all-pass filter when connected to the next stage. The best result is obtained when combining asymmetry of the network with the inclusion of two additional resistive elements, achieving a quadrature error lower than$2.0^{\circ}$and a magnitude error lower than of 0.17 from 17 GHz to 22 GHz at the output of the quadrature all-pass filter. As an application, it has been proven that the RMS phase error at the output of a 5-bit active phase shifter has been decreased from$7.6^{\circ}$to$2.3^{\circ}$.

In this paper the potential of CMOS technology will be applied to the design of a new programmable gain amplifier (PGA), for its use in a phase shifter for an array antenna receiver operating over the 18-27 GHz frequency range. The main blocks that will provide the required phase shift are a quadrature signal generator (QSG) followed by a programable gain amplifier (PGA). In addition, the next stage to the phase shifter, consisting of a power combiner, will be added to the design to achieve a better reproduction of the output signal behavior. The PGA topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.5º for the phase and 0.76 dB for the gain.

This paper presents the design of a new phase shifter using 65 nm CMOS technology, for its use in a receiver array of antennas operating at the K band (24 GHz). The desired phase shift is obtained by the operation of two main blocks: a quadrature all-pass filter (QAF) and a voltage gain amplifier (VGA). This topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.55º for the phase and 0.78 dB for the gain.