This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This paper presents an all-NMOS RF-DC rectifier with internal$V_{\mathrm {TH}}$cancellation (IVC) technique to achieve an ultra-wide high-PCE input power range for RF energy harvesting. The all-NMOS topology replaces the PMOS transistor in the conventional cross-coupled rectifier with a diode-like NMOS transistor to obtain the maximum current driving capability while effectively reducing the reverse leakage current at higher input power, combining the strengths of diode-based and cross-coupled rectifiers. The IVC unit is used to compensate for the threshold voltage of the diode-like rectifying transistor on the output side and improve the PCE at low input power. As a result, the sensitivity and the input power range are improved simultaneously. The proposed rectifier is fabricated with a 0.18-$\mu $m standard CMOS technology. The measurement results show that the IVC all-NMOS rectifier achieves 55% PCE, −15.5 dBm sensitivity and 18.6 dB input power range when operating at 900 MHz with a 30 k$\Omega $load.

This brief presents a high-sensitivity battery-free radio frequency (RF) energy harvesting system with ultralow-power auxiliary modules. The proposed design implements two-stage energy conversion based on burst charging mode, achieving ultrahigh sensitivity by using an intermittent charging method that eliminates the charge pump’s loading effect on the RF rectifier. An all-nMOS RF--dc rectifier with internal${V}_{\mathrm {TH}}$cancellation (IVC) technique achieves an ultrawide high-power conversion efficiency (PCE) input power range for an RF energy harvesting. Furthermore, a${V} _{\mathrm {TH}}$-based voltage reference is introduced, enabling subthreshold operation of transistors with picowatt-level power consumption, thereby simultaneously improving both PCE and sensitivity. The proposed RF energy harvesting system is implemented with a 0.18-$\mu $m standard CMOS technology. The results show that the system achieves a 55% PCE, a −33-dBm sensitivity, and a 17-dB input power range at 2.4 GHz.

This paper presents a 6.78MHz reconfigurable four-phase dual-output series resonant rectifier that integrates hysteresis control and the triple-mode double-frequency current wave modulation (DFCWM) technique. The rectifier accomplishes AC-DC rectification and dual-output voltage regulation within a single power stage, achieving high efficiency and a reduced number of off-chip components. The combination of hysteresis control with the triple-mode DFCWM enables rectification and voltage regulation without crossover adjustments through four independent phases. Without altering the external LC resonant frequency, more uniform power conversion and reduced output voltage ripple are achieved, while also enhancing the transient response speed of the load. When simulating with a 0.18-μm CMOS process, the dual-output voltages can be adjusted to 1.1V and 2.2V, reaching a maximum output power of 0.7W with a peak power conversion efficiency (PCE) of 89.2%. Furthermore, a rapid transient load response can be observed when the load current varies between 20mA and 200mA.

This paper presents a self-powered parallel synchronized switch harvesting on inductor (P-SSHI) active rectifier with an energy-efficient adaptive switch control circuit. The energy-efficient adaptive switch control circuit reuses comparators within the active rectifier for both zero-crossing detection and voltage flipping detection, simplifying the switch control module. The proposed active rectifier incorporates an active diode and a MOSFET within each energy transfer path to mitigate the forward voltage drop across rectifying elements. The proposed P-SSHI circuit which includes a diode in each voltage flipping path shows high adaptability to different inductances. All the auxiliary circuits are powered by the storage capacitor. The proposed circuit is designed in 180 nm CMOS process, and the total occupied chip area is 0.18 mm2. The power dissipation of the switch control module is only 0.15 μW, owing to its simplicity. The simulation results show that the proposed design achieves a high voltage flipping efficiency of 85.4%. The maximum output power is 5.5 times greater than that of the ideal full-bridge rectifier.

This paper proposes a dual-path CMOS RF-to-DC rectifier operating at 2.45-GHz with an ultra-wide high power conversion efficiency (high-PCE) input range. A new rectifier based on all NMOS rectification devices (all-NMOS) is proposed for high-power path and a modified cross-connected (CC) rectifier is designed for low-power path. The control signal for path switching is adaptively generated by auxiliary circuits without external reference or supply. The input power range with high-PCE is extended by the proposed architecture to meet the various application scenarios of energy harvesting. Implemented in a 0.18-μm standard CMOS technology, the proposed dual-path rectifier achieved a sensitivity of −20.7dBm, and it has two peak PCEs of 57% and 62% at −15dBm and 1.6 dBm, respectively. Furthermore, the PCE of the proposed dual-path rectifier can be maintained above 20% with a 27 dB input range from −22 to 5 dBm when operating at 2.45-GHz with a 50-k$\Omega$ load.