Tri-level current-steering digital-to-analog converters (DACs) offer an appealing balance between resolution and static linearity, making them attractive to be employed as feedback DAC in high-resolution continuous-time Delta-Sigma-Modulator (CTDSM). However, they are susceptible to non-linearity caused by dynamic, signal-dependent switching errors degrading the overall performance. While such errors have been thoroughly analyzed in literature for single-bit current-steering DACs, they have not been thoroughly investigated for tri-level current-steering DACs. As a result, this paper investigates the sources of these errors and demonstrates their severity by analysis and simulations employing a tri-level DAC in an exemplary CTDSM. In addition, techniques for mitigating dynamic errors, including device sizing and switching schemes, are discussed to help mitigate the non-linearity.

This work links Ring Oscillator (RO)-Physical Unclonable Function (PUF) specific design parameters with previously neglected area consumption per PUF bit. In prior art, the PUF specific design parameters such as number of ROs in a given RO collection that can be compared to one another and readout time are optimised in terms of e.g stability and/or power consumption. The influence of these design parameters on the effectively required area per bit remains overlooked, since optimization on area is mostly done simply by designing small ROs. This work establishes a relationship between the general design parameters and the area per bit for RO-PUFs. Using finite frequency readout resolution by means of a limited readout time, the RO-PUF is transformed into graph-theory and by finding a Minimum Spanning Tree (MST), the best possible yield of a given collection of ROs is determined. The given collection together with variable yield is then mapped to a certain demand on area per bit. An extensive yield analysis is performed which then is again mapped to a certain area per bit, leading to the proposed connection between readout time, amount of ROs in a collection and area per bit.The system-level analysis performed shows that a set of 8 ROs represents a sweet-spot in terms of area per bit as well as low read-out time.

Transimpedance amplifiers (TIAs) are used in a wide variety of low noise current sensing frontends. A recently proposed mixed-signal TIA (MS-TIA) is an extension of the integrator-differentiator TIA but including digitization and digital differentiation. However, the MS-TIA requires a high resolution analog-to-digital converter (ADC) in order to maintain good sensitivity. Capacitive digital-to-analog converter (C-DAC) based successive approximation register (SAR) ADCs achieve high resolution at medium bandwidth with good power efficiency, however require a power hungry ADC input driver. In this paper, a combination of the MS-TIA and a modified C-DAC reset scheme is presented, which eliminates the need for a high performance ADC input driver, resulting in major improvements regarding power consumption and linearity. The results are verified by transistor level simulations in a standard 180nm CMOS technology.

The project VE-FIDES will contribute with a solution based on an innovative multi-level fingerprinting approach to secure electronics supply chains against the threats of malicious modification, piracy, and counterfeiting. Hardware-fingerprints are derived from minuscule, unavoidable process variations using the technology of Physical Unclonable Functions (PUFs). The derived fingerprints are processed to a system fingerprint enabling unique identification, not only of single components but also on PCB level. With the proposed concept, we show how the system fingerprint can enhance the trustworthiness of the overall system. For this purpose, the complete system including tiny sensors, a Secure Element and its interface to the application is considered in VE-FIDES. New insights into methodologies to derive component and system fingerprints are gained. These techniques for the verification of system integrity are complemented by methods for preventing reverse engineering. Two application scenarios are in the focus of VE-FIDES: Industrial control systems and an automotive use case are considered, giving insights to a wide spectrum of requirements for products built from components provided by international supply chains.

This paper presents a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma Modulators. The feedback DAC in DSMs is usually a performance bottleneck, as all of its errors directly add at the input node. Fore - or background error correction based on LUT can efficiently eliminate the DAC errors, but can also impose significant circuit overhead in the digital and analog domain. The presented method reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.