This paper presents an analytical study and modeling of the Helical ladder switched capacitor converters (HLSC). The higher output impedance (ROUT) problem in the conventional ladder switched capacitor converter (CLSC) is addressed in the HLSC by identifying the large charge carrying flying capacitors of CLSC and reconfiguring them to reduce the charge flow. A systematic process is proposed to develop an HLSC architecture for any given voltage conversion ratios (VCR) using its equivalent CLSC architecture. As the switched capacitor converter (SCC) performance mainly depends on the ROUT, analytical models are developed to calculate the ROUTusing switching frequency (fSW), total flying capacitance (Ctot), and load current (IL) for an n-stage HLSC and CLSC. From these models, the variation of charge sharing loss and parasitic capacitance loss, and their impact on the efficiency (η) and output voltage (VOUT) is analyzed across all the VCRs. The comparison between CLSC and HLSC results shows that the HLSC has superior performance over CLSC. The developed models are useful for comparing the different performance metrics of various SCC topologies.

This paper presents a sub$-V_{\text{TH}}$ring oscillator (RO) based digital temperature sensor where the ROs are designed using the sub$-V_{\text{TH}}$transmission gates (TG). Two ROs are designed with different TGs to generate$f_{\mathrm{H}}$and$f_{\mathrm{L}}$frequencies, whose frequency ratio$(f_{\mathrm{H}}/f_{\mathrm{L}})$increases linearly with temperature. The temperature-dependent$f_{\mathrm{H}}/f_{\mathrm{L}}$ratio is converted to digital code (TCODE) using two asynchronous counters. Further, a cascoded 3T regulator is proposed to power the sensor and reduce its line sensitivity. The sensor prototype is designed in 180 nm while operated at 0.7 V supply it consumes 7.7 nW of power (3.6 nW by core and 4.1 nW by digital block) with$-1.5^{\circ}\mathrm{C}/+1.94^{\circ}\mathrm{C}$inaccuracy across 0°C to 100°C range after 2-point calibration at 10°C and 80°C. It achieves an 0.15°C resolution and FoM of 19 pJ-K2with 1.28 ° C/V line sensitivity when operated from 0.7 V to 2.2 V supply voltage.

This paper presents a current reference using temperature-compensated CMOS resistors. In the proposed circuit, the constant current is generated by compensating complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) CMOS resistors. The CMOS CTAT resistor is designed using a MOS biased in the deep-triode region. In contrast, the PTAT resistor is derived using the MOS biased in the sub-threshold triode region with a$\boldsymbol{V}_{\mathbf{TH}}-\mathbf{tracking}$voltage. The reference current is generated using a 3T regulator and the temperature-compensated CMOS resistors. The sensor prototype is designed in 180 nm for 172 pA of reference current$(\boldsymbol{I}_{\mathbf{REF}})$at a temperature coefficient (TC) of 327 ppm/ ° C from 0 ° C to 80 ° C. It has 0.63 nW power consumption at 1.1 V supply with an average line sensitivity of 0.63 %/V when operated from 1.1 V to 2.1 V supply voltage.

This paper presents a hybrid multiphase interleaving technique for bottom plate parasitic charge sharing and ripple reduction in SC converter (SCC). The proposed technique uses multiphase interleaving for reducing ripple and scalable parasitic charge redistribution technique for reducing bottom plate parasitic loss, and incorporates them to achieve both features. An 8-core, 8-phase interleaved 1/2 SCC with 3 charge redistribution steps is derived using the proposed technique and implemented in the 180 nm CMOS process. Post-layout simulations of 8C8P validate that the proposed hybrid technique achieves 83% efficiency and 50% lesser ripple than the existing SPCR technique with the same flying capacitance and switch conductance.

A 0.13 nW ultra-low-power over-temperature-protection circuit is proposed for highly integrated System-on-Chips (SoC). The circuit detects a temperature of $120^{\circ} \text{C}$ but can be programmed for other temperature thresholds. The temperature detection is achieved by comparing a reference voltage with a 2-transistor ultra-low-power inverter architecture. The 2transistor inverter is designed to have a proportional-to-absolute-temperature (PTAT) threshold characteristic, and the reference voltage is generated on-chip with a 2-transistor reference. The design is implemented in $0.18 \mu \text{m}$ CMOS technology and occupies an area of $0.0117 \text{mm}^{2}$. The design operates from 0.5 V supply voltage and has a line sensitivity of $0.1^{\circ} \text{C}/\text{V}$ and a hysteresis width of $7.7^{\circ} \text{C}$, as seen from simulations. The trim-free design has a worst-case process variation of 4%.