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Yulin Tang

dblp:333/6844 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0009-7850-0631ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% Processor architecture and microarchitecture · 13%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels
fault attacks
0.912025
ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching · MICRO 2025
Hardware security and side channels › fault attacks › fault injection attack
rowhammer attack
0.912025
ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching · MICRO 2025
Memory systems
DRAM
0.912025
ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching · MICRO 2025
Memory systems › memory controller
DRAM address mapping
0.912025
ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching · MICRO 2025
Processor architecture and microarchitecture
speculative execution
0.312025
ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching · MICRO 2025

Methods — techniques the papers use, named apart from their topics

pseudo-barriers · 1.7prefetch-based hammering · 1.7multi-bank parallelism · 1.7control-flow obfuscation · 0.9control flow obfuscation · 0.9
YearPublicationVenuePosition
2025 ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching
abstract
Rowhammer is a critical vulnerability in dynamic random access memory (DRAM) that continues to pose a significant threat to various systems. However, we find that conventional load-based attacks are becoming highly ineffective on the most recent architectures such as Intel Alder and Raptor Lake. In this paper, we present $ρ$Hammer, a new Rowhammer framework that systematically overcomes three core challenges impeding attacks on these new architectures. First, we design an efficient and generic DRAM address mapping reverse-engineering method that uses selective pairwise measurements and structured deduction, enabling recovery of complex mappings within seconds on the latest memory controllers. Second, to break through the activation rate bottleneck of load-based hammering, we introduce a novel prefetch-based hammering paradigm that leverages the asynchronous nature of x86 prefetch instructions and is further enhanced by multi-bank parallelism to maximize throughput. Third, recognizing that speculative execution causes more severe disorder issues for prefetching, which cannot be simply mitigated by memory barriers, we develop a counter-speculation hammering technique using control-flow obfuscation and optimized NOP-based pseudo-barriers to maintain prefetch order with minimal overhead. Evaluations across four latest Intel architectures demonstrate $ρ$Hammer's breakthrough effectiveness: it induces up to 200K+ additional bit flips within 2-hour attack pattern fuzzing processes and has a 112x higher flip rate than the load-based hammering baselines on Comet and Rocket Lake. Also, we are the first to revive Rowhammer attacks on the latest Raptor Lake architecture, where baselines completely fail, achieving stable flip rates of 2,291/min and fast end-to-end exploitation.
Shan Tang, Yulin Tang, Xiapu Luo, Yinqian Zhang, Weizhong Qiang
MICRO3