Three-dimensional (3-D)nandflash memory has emerged as the predominant solution for high-capacity nonvolatile data storage. However, the continuous increase in storage density has concurrently led to significant challenges in data reliability degradation. This article investigates the application of polar codes for error correction innandFlash memory. We propose a combined Monte Carlo (CMC) method to dynamically determine information bit positions in polar code encoding for flash memory chips under varying reliability statuses. For decoding, we identify that the hard-decision read mechanism in flash memory introduces extreme log-likelihood ratio (LLR) quantization effects. This quantization phenomenon may erroneously prune correct decoding paths during successive cancellation list (SCL) decoding, thereby degrading the error correction capability of polar codes. To address this critical issue, we develop a cascaded parity-check (PC)-assisted path pruning scheme integrated with the SCL algorithm. The experimental results demonstrate that the proposed polar code algorithm can significantly enhance the reliability of data storage innandflash memory. In the long code length scenario, the proposed polar decoding scheme with PC-assisted pruning achieves a maximum uncorrectable bit error rate (UBER) reduction of 98.62% compared to algorithms without PC. The proposed approach demonstrates an 8.56 times increase in the raw bit error rate (RBER) threshold for achieving 100% error correction success, significantly surpassing the performance of conventional low-density parity-check (LDPC) codes, especially toward the end of the flash memory’s lifespan.

Low-density parity-check (LDPC) codes are now broadly employed as error correction code (ECC) solutions in NAND flash memories. With the rapid development of high-performance three-dimensional (3-D) NAND memories, mitigating the read latency caused by LDPC decoding attempts has emerged as an investigation focus. Existing investigations have demonstrated that efficient memory sensing is crucial to enhancing the efficiency of LDPC decoding attempts. The optimal memory sensing parameter options are determined by the threshold voltage distributions of NAND flash, which are difficult to be dynamically extracted during data retention. To address the issue, this article proposes an online lightweight strategy for threshold voltage distribution estimation, named LVDE. LVDE suggests a probe wordline design that uses one-read sampling to measure the threshold voltage distributions during long-term retention. Further, LVDE develops a methodology for the cross-layer estimation of threshold voltage distributions, thereby utilizing the measurements of the probe wordline to estimate those of each layer. LVDE is implemented on real flash chips to compare with numerous state-of-the-art strategies. Experimental results demonstrate that LVDE can significantly enhance the efficiency of LDPC decoding attempts and thus improve the read performance of 3-D NAND flash memory.

Resistive random access memory (RRAM)-based in-memory computing (IMC) architectures are currently receiving widespread attention. Since this computing approach relies on the analog characteristics of the devices, the write variation of RRAM can affect the computational accuracy to varying degrees. Conventional write–verify (W&V) procedures are performed on all weight parameters, resulting in significant time overhead. To address this issue, we propose a training algorithm that can recover the offline IMC accuracy impacted by write variation with a lower cost of W&V overhead. We introduce a importance-driven weight allocation (IDWA) algorithm during the training process of the neural network. This algorithm constrains the values of less important weights to suppress the diffusion of variation interference on this part of the weights, thus reducing unnecessary accuracy degradation. Additionally, we employ a layer-wise optimization algorithm to identify important weights in the neural network for W&V operations. Extensive testing across various deep neural networks (DNNs) architectures and datasets demonstrates that our proposed selective W&V methodology consistently outperforms current state-of-the-art selective W&V techniques in both accuracy preservation and computational efficiency. At same accuracy levels, it delivers a speed improvement of$6\times \sim 32\times $compared to other advanced methods.

With the explosive growth of data storage demands, the storage density of flash memory continues to increase. However, the reliability and read performance of high-density flash memory are constantly declining. To address this issue, this study proposes a low-cost read reference voltage (RRV) calibration strategy based on random bit flips. In this study, the relationship between the random bit flips count (RFBC) of flash memory and the read reference voltage offset level (RRVOL) is characterized, and an RFBC-RRVOL conversion model is constructed. Subsequently, the characteristics of 3D flash memory RRV offset are thoroughly studied, and based on the observation results. A RRV grouping optimization scheme and RRV calibration range WL expansion scheme are proposed to achieve generalized calibration of all WLs in flash memory blocks. Experimental results indicate that the proposed strategy introduces a minimal storage overhead of only 15.26 KB, which reduces the raw bit error rate (RBER) of flash memory at the end of life (EOL) and increases the success rate of one time read to 99.89%. Such improvements greatly enhance the reliability of data storage and reading performance. These results demonstrate that the strategy has good practicality and effectiveness in addressing the reliability and read performance issues of high-density flash memory.

The 3-D flash memory is gradually becoming the mainstream nonvolatile storage medium due to its high capacity and high performance. However, interlayer interference during 3-D flash programming leads to significant differences in the error characteristics of edge and inner word lines; interlayer interference becomes more pronounced as the number of stacked layers increases, seriously affecting data storage reliability. In this study, many actual tests were conducted on triple-level cell (TLC) and quad-level cell (QLC) flash memory, which are the mainstream storage media in the current consumer market, to obtain the edge and inner word-line threshold voltage data under the interference of different factors, such as retention loss and read disturb; then, the threshold voltage difference between the edge and inner word lines under different conditions was quantitatively analyzed. An edge word-line reliability optimization strategy is proposed based on the read-reference voltage extra offset (RRVEO). Experimental results show that this strategy can reduce the edge word-line raw bit error rate (RBER) by more than 90% and eliminate the reliability difference between inner and edge word lines without significant overhead, thus significantly improving the data storage reliability of flash memory.

With the wide application of NAND flash storage systems in read-intensive memory, the corresponding reliability enhancement strategies for mitigating read disturb become the focus of investigations in recent years. The prior investigations have reported the strategies based on data modulation and verified their effectiveness in mitigating retention loss. The most significant advantage of these strategies is that they can often achieve significant reliability enhancement effect with great read performance, since they are usually based on asymmetric coding. This feature means that they have the potential to be ideal reliability enhancement strategies for read-intensive memory applications. To propose a universal and highly reliable data storage strategy, this article first observes the error modes at the cell-state level under the reliability stresses of retention loss and read disturb with floating-gate (FG) 3-D triple-level (TLC) NAND flash, and then proposes a target cell states elimination (TCSE) coding strategy for further restraining bit errors. In addition, this article for the first time reports the extra bit errors generated in the decoding process of the storage strategies based on data modulation, and defines the concept of transfer factor (TF) for evaluation. By using the proposed TCSE, the experimental results show that the overall bit error rate (BER) can be reduced by 80%–90% on average, compared with the raw random data pattern.