The development of large language models (LLMs) has catalyzed unprecedented demand on the computing network, specifically for large-scale, few-hops, and low-latency, which directly underpin LLM task efficiency. However, mainstream topologies such as Clos suffer from costs and latency, while topologies with good scalability have symmetric or collective communication issues. In order to achieve a favorable balance among design metrics, we propose a novel topology named the Balanced Sparse Tree (BST), which is a topology characterized by symmetric design and sparse connections, motivated by hypergraph theory and Steiner Systems. Its degree-diameter upper-bound approaches the Moore Bound for Bipartite Biregular graphs, larger than other known dia-meter-2 topologies. Furthermore, we incorporate differentiated routing, deadlock freedom, and topology-affined deployment into BST. Testbed experiments, simulations, together with modeling analysis, demonstrate the superiority of BST over the state-of-the-art in network scale, latency, bandwidth, and cost. With equivalent scales, BST outperforms Clos with a 50% cost reduction while maintaining comparable performance for AI workloads. Furthermore, BST delivers a 3.9%–11.8% gain in collective communications and has 13.4% improvement over state-of-the-art topologies.

Nowadays, the performance of data-center networks (DCNs) has become crucial for advancing large-scale computing applications. Hence, to improve the throughput, energy-efficiency and latency of DCNs, people are trying to replace the electrical packet switching (EPS) based spine switches with optical circuit switching (OCS) based ones. In an OCS-based DCN, topology engineering (TPE) is the key operation to dynamically reconfigure its inter-pod topology for accommodating traffic with optimized resource utilization. TPE consists of two highly-correlated steps, i.e., optimizing the target physical inter-pod topology of the DCN based on a traffic matrix, and planning the procedure of OCS reconfiguration such that hitless transition can be achieved. In this paper, we study how to optimize the two steps jointly to efficiently accelerate the hitless reconfiguration of an OCS-based DCN. We formulate a mixed linear programming model (MILP) to solve the joint optimization exactly. Then, to solve the problem time-efficiently, we propose an approach that optimizes TPE design greedily according to various metrics to minimize the number of stages required in hitless reconfiguration for TPE. Extensive simulations verify the effectiveness of our proposals and demonstrate their benefits over existing benchmark.

Designing a disassembly line layout is an important part of the recycling process of end-of-life products. Parallel disassembly lines have the characteristics of high disassembly efficiency and can disassemble multiple different products simultaneously. This work formulates a mathematical model for optimizing such lines in terms of disassembly profit and the number of skills. It also proposes an improved bat algorithm based on the Pareto principle to solve the model. In order to verify the effectiveness and feasibility of the proposed algorithm, it is compared with the non-dominated sorting genetic algorithm and a decomposition-based multi-objective evolutionary algorithm. Experimental results indicate that this algorithm has outstanding solution capability and is thus suitable for solving parallel disassembly line balance problems.