Field-Programmable Gate Arrays (FPGAs) are extensively utilized in various fields due to their inherent flexibility and ability to be reconfigured. The functionality of digital designs within FPGAs is stored as configuration frames within the bitstream. Previous studies introduced tools like BIL, RapidSmith, Debit, DAT and BitFREE, which reverse-engineer the bitstream to reveal the Boolean logic of Look-Up Tables (LUTs) using the Xilinx ISE design suite. This tool produces both the bitstream and a textual representation of the placed design in the form of the Xilinx Design Language (XDL) file, enabling deeper insights into the FPGA’s internal structure. However, with the introduction of the AMD Xilinx Vivado design suite, support for XDL and text-based hardware adjustments discontinued, making it more challenging to reverse-engineer modern bitstreams. Our prior study, REVBiT, utilized the AMD Xilinx Vivado Design Suite, which extracted the LUTs and identified Boolean logic but failed to identify the pin combination in its present form. The pin combination of LUTs is also essential information for determining the correct configuration of LUTs in the bitstream. To address the limitation of state-of-the-art methods, we introduce REVBiT 2.0, a methodology for extracting LUTs and their Boolean logic, along with the pins connection of the LUT. Our proposed deep-learning models have been trained and tested with 92,82,950 data samples for the pin combination and Boolean logic identification. The experiment for bitstream extraction is carried out on a real FPGA board with the help of a logic analyzer. Our proposed methodology has been experimentally validated on AMD Xilinx 7-Series, Ultrascale, and Ultrascale+ FPGA device families for 2, 3, and 4-input LUTs using the AMD Xilinx Vivado design suite and relying on bitstream without any additional information. We achieved ≈ 100% accuracy for the LUT extraction, more than 87.50% prediction accuracy for pin combination and 92.43% for Boolean logic identification from the bitstream.

Age prediction for integrated circuits (ICs) is essential in establishing prevention and mitigation steps to avoid unexpected circuit failures in the field. Any electronic system would get benefit from an accurate age calculation. Additionally, it would assist in reducing the amount of electronic waste and the effort toward green computing. In this article, we propose a methodology to estimate the age of ICs using the Gaussian process regression (GPR). The output frequency of the ring oscillator (RO) is influenced by various factors, including the trackable path, voltage, temperature, and ageing. These dependencies are leveraged in the GPR model training. We demonstrate the RO’s frequency degradation by employing the Synopsys HSPICE tool with 32 nm predictive technology model (PTM) and the Synopsys technology library. We used temperature variation from 0 °C to 100 °C and voltage variation from 0.80 to 1.05 V for the data acquisition. Our methodology predicts age precisely; the minimum prediction accuracy with a month deviation on linear sampling rate is 85.36% for 13-Stage RO and 87.09% for 21-Stage RO, with a range of improvement in prediction accuracy compared to state-of-the-art (SOTA) is 9.74% to 16.99%. Similarly, on the logarithmic sampling rate, the prediction accuracy for 13-Stage RO and 21-Stage RO are 98.62% and 98.56%, respectively. The proposed methodology performs more accurately in terms of prediction accuracy and age prediction deviation from the SOTA methodology.

The presence of counterfeit recycled ICs (CRICs) in the global semiconductor supply chain is a major concern in the present-day world. These CRICs are less reliable and have become a serious threat to the ICs employed in safety–critical systems. Accurate age prediction for integrated circuits (ICs) is crucial for implementing preventative and mitigation strategies to avoid unexpected failures in the field. By precisely estimating the age of an IC, electronic systems can benefit from improved reliability and performance, as maintenance and replacements can be scheduled proactively, and reducing the risk of sudden breakdowns. Furthermore, accurate age prediction plays a vital role in extending the lifespan of electronic devices, which in turn helps to minimize electronic waste. This not only reduces the environmental impact but also supports the broader goal of green computing by promoting more sustainable and resource-efficient technology practices. In this article, we introduce a method for detecting a CRIC and estimating its age by utilizing the existing input-output (IO) pad structures targeting sensorless chips. The proposed methodology estimates age by measuring the voltage drop across the protection diodes present in the IO pad structure and applying this voltage drop to the proposed polynomial regression model. This methodology requires no additional sensory circuit, resulting in no area overhead. As there is no requirement for a special on-chip sensor, the proposed methodology can be used to detect the age of an IC in production. Our proposed polynomial regression model achieves a mean squared error (MSE) of 1.77 h, with a minimum improvement of 99.7% over the state-of-the-art methodologies.

Field-Programmable Gate Arrays (FPGAs) are widely used in various applications due to their flexibility and reconfigurability, and they store the functionality of digital design in the form of configuration frames within the bitstream. In the earlier studies, state-of-art methodologies, such as BIL and RapidSmith reverse engineer the bitstream to identify the boolean logic of LUTs using the Xilinx ISE tool, which provides bitstream and textual information of placed design in the form of a Xilinx Design Language (XDL) file. However, the more recent tool, Xilinx Vivado, does not include XDL support or text-based hardware adjustments. To resolve the above problem, here we introduce a methodology called REVBiT for LUT extraction and boolean logic identification that offers the potential to verify functionality against a trusted reference or rectify corrupted bitstream data by correcting it. Also, our propose methodology verified on AMD Xilinx 7-Series, Ultrascale and Ultrascale+ device families FPGAs using the Xilinx Vivado tool and does not rely on additional information besides the bitstream. We achieved 100% accuracy for the LUT extraction and 93.86%, 96.26%, and 95.16% accuracy for the boolean function identification for 7-Series, Ultrascale and Ultrascale+ device families, respectively.