In this work, we present single-event upset (SEU) analysis for Forksheet FET (FSFET) based CMOS circuits. Next, we present an array-level power and performance analysis along with the Vminevaluation for the FSFET-based SRAM. Physics based TCAD and industry-standard BSIM-CMG compact models are calibrated for accurate circuit analysis in SPICE. The impact of varying Heavy-Ion Radiation (HIR) doses and strike orientations is investigated for the FSFETs. The robustness of CMOS inverter against HIR is also reported in terms of failure time (tfail) and output voltage swing ($Δ$VDrop). For the SRAM, we determine the critical Linear Energy Transfer (LET). For FSFET, the individual n-/p-FETs are more vulnerable to the irradiation incident on nearby devices. At the circuit level, in comparison to perpendicular strikes, the$Δ$VDropincreases by 1.25V and 2.75V respectively, for oblique and transverse incidences, at a dose of 2.0MeVcm2/mg. The tfail also increases by 43% and 60% and the SRAM critical LET also decreases by 85% and 57.5%, respectively. The array level SRAM evaluation shows that the FSFET enables reliable operation with low-power consumption, impressive noise margins, and low minimum operating voltage (Vmin) values. FSFET SRAM power dissipation during the read and write operations is as low as 7.02$μ$W, and 3.00$μ$W respectively. At VDD=0.70V, the noise margins for hold, read, and write operations are 289.27mV, 122.89mV, and 297.79mV. The Vminfor read and write operations are 0.30V and 0.35V respectively.

As CMOS scaling approaches its fundamental limits, the explosive rise of AI and LLMs has unveiled profound bottlenecks in computing architectures. This paper presents two groundbreaking paradigms poised to reshape the landscape of high-performance computing and meet the surging demands of AI-driven workloads. The first paradigm is 3D monolithic integration, a revolutionary approach that achieves unprecedented logic density through Complementary FETs (CFETs), where pMOS and nMOS transistors are vertically stacked, and a dramatic expansion of on-chip memory capacity by integrating memory layers atop logic transistors. The second paradigm leverages the transformative potential of operating chips at cryogenic temperatures where transistors exhibit enhanced performance, and parasitic resistances are substantially minimized. These advancements hold the promise of redefining computing efficiency and performance for the AI era.

As transistor scaling advances into the sub-3 nm regime, self-heating effects (SHE) and aging-induced degradation emerge as profound challenges that threaten timing closure, signal integrity, guardbands, and long-term reliability. This work presents a comprehensive transistor-to-GDS reliability analysis that captures the impact of SHE and aging in nanosheet field-effect transistors (NSFETs) and propagates it through the entire design stack to full-chip signoff. We evaluate a 64-bit RISC-V processor core and an AI accelerator containing 4096 Multiply-and-Accumulate (MAC) units, both implemented using gate-all-around (GAA) NSFET technology. TCAD simulations, carefully calibrated against measurement data, reveal local temperature rises up to 124 K in multi-stack sheet structures, which exacerbate aging and result in a threshold voltage shift of up to 42.3 mV. Incorporating these effects into standard cell characterization and commercial signoff timing analysis uncovers substantial End-of-Life (EOL) timing degradation—37.7 % for the RISC-V core and 61.7 % for the AI accelerator—highlighting the urgent need for SHE- and aging-aware methodologies, as well as reliability-optimized standard cell libraries for advanced nodes.