With the advent of next-generation networks, new applications across multiple domains are gaining traction. This shift demands a redefined network paradigm, where ultrareliable, low-latency communication is key. In this work, we explore and extend the concept of in-network programmability in new directions. Unlike conventional approaches, we leverage P4 data plane programmability to implement an in-network collision avoidance algorithm in a UAV scenario. We evaluate our hardware-based implementation under different conditions, including latency and velocity, demonstrating that it efficiently detects and prevents collisions. Our results show the impact of end-to-end latency and highlight how in-network processing can be a valuable ally for time-sensitive tasks, paving the way for future advancements in hardware-based in-network applications.

Remote Direct Memory Access (RDMA) is a key technology in modern data centers, enabling low-latency and high-throughput communication. However, evaluating RDMA performance and validating network designs often requires costly hardware setups or simulation tools with limited performance and realism. In this work, we present P4DMA, a system that leverages programmable switch ASICs to generate realistic high-performance RDMA traffic. By implementing RDMA traffic patterns using the P4 language, P4DMA enables researchers and practitioners to generate RDMA workloads at line rate, without relying on traditional RDMA NICs (RNICS). With Tofino's traffic generation capacity of up to Tbps, P4DMA offers a novel approach to stress and evaluate RDMA-capable infrastructures, and accelerate the prototyping of new RDMA-based applications.

The increasing demand for real-time industrial applications demands deterministic communication across networked devices. Time-sensitive networking (TSN) offers reliable performance to meet these requirements, compatible with the current Real-Time Ethernet (RTE) solutions applied in the industry. While TSN ensures determinism inside Ethernet networks, its integration with 5G/6G wireless technologies can overcome flexibility limitations. This paper explores key challenges in integrating TSN with mobile networks, focusing on device synchronization and flow mapping. We introduce a tool aligned with the 3GPP specifications that covers time synchronization across TSN domains via 5G and implements flow mapping based on application-specific quality of service (QoS) requirements. We evaluate these features under various scenarios, including a use case for an industrial production line use case. Our solution is developed as an open-source framework for the OMNeT++ simulator, supporting reproducibility and continuous updates and paving the way for customizable network solutions.

Accurate time synchronization is essential for emerging networked applications that demand low latency, high precision, and coordinated operations, such as those found in data centers, time-sensitive networking (TSN), and distributed systems. In this demo, we introduce P4Timely, a flexible and programmable framework designed to evaluate and prototype time synchronization protocols in real time. Built using P4 and commodity programmable hardware, P4Timely enables users to easily configure synchronization settings through a simple interface, specify network conditions such as delay, jitter, and packet loss, and define whether nodes act as synchronizing or synchronized entities. P4Timely supports dynamic reconfiguration at runtime and provides built-in monitoring tools to assess synchronization accuracy under diverse network conditions.

In-Network Computing (INC) is transforming how we design and evaluate modern networks by enabling programmable data planes to execute computational tasks at line rate. However, deciding which functions to offload, to which device and using which strategy is not a trivial task. This PhD project explores the opportunities, challenges and boundaries of offloading network functions and application logic to programmable switches and SmartNICs. Through a series of case studies, we demonstrate that INC-based solutions enhance both network efficiency and application performance. On the other hand, we also demonstrate the tradeoffs of these offloadings and how they can impact the infrastructure in terms of performance and resource utilization. Our findings provide actionable insights for the deployment of INC in real-world scenarios, highlighting where offloading delivers the most value and where traditional approaches remain preferable.

The pursuit of self-driving networks is increasing pressure on adopting intelligent, edge-based networking services. However, deploying autonomous network models within operational and large-scale infrastructures entails substantial risks that require rigorous verification and validation procedures. In this context, the application of a Network Digital Twin (NDT) is emerging as a viable approach towards intelligent network decision-making based on high-fidelity models built upon digital representations of physical network devices (i.e., Digital Twins). In this paper, we take the first steps towards efficiently provisioning NDT models. To that end, we introduce the Digital Twin Network Provisioning Problem (DigiNet), which encompasses the optimal placement of NDT models and the efficient collection of telemetry data for synchronizing NDT models with their physical counterparts. We theoretically formalize DigiNet as a Mixed-Integer Linear Programming (MILP) model and present a polynomial-time heuristic. Our results show that DigiNet outperforms baseline approaches by up to 10x regarding the number of NDT models provisioned.

In recent years, the increasing demand for network resources due to real-time applications and data-intensive activities has posed challenges in managing and optimizing network performance. To assess network performance, security, and efficiency, traffic generation plays a crucial role. We introduce PIPO-TG, a Tofino-based traffic generation for high-performance experiments. The primary objective of PIPO-TG is to generate realistic and diverse traffic patterns, enabling researchers to evaluate network performance under varying conditions providing customizable packet forwarding with P4 programmable data planes. Our main contributions include user-defined packet header customization and open-source code for reproducibility. These efforts foster collaboration within the research community to advance traffic generation techniques. We show that PIPO-TG only requires a few lines of code to simulate heterogeneous network scenarios (e.g., traffic bursts and DDoS attacks) while maintaining hardware performance and flexibility.

Network emulation traditionally relies on software-based solutions. While extremely useful in many scenarios, it suffers from performance fidelity and inherent scalability constraints. With the advent of P4 and programmable switches like Tofino, new opportunities for hardware-based network emulation are emerging. P7 (P4 Programmable Patch Panel) offers a solution for high-fidelity 100G traffic network emulation, including different link characteristics such as latency, jitter, packet loss, and bandwidth, as well as the ability to define custom topologies. However, it currently lacks support for custom P4 code in emulated devices. This is where multiple pipelines network emulation comes in. In this demonstration, we show how to emulate a topology using P7 and incorporate custom P4 code into each emulated node. We allocate a dedicated pipe for user-defined P4 code and allow users to conFigure tables for each node separately.

In recent years, advances in virtual reality (VR) technologies (e.g., high-quality VR headsets) have enabled a new perspective of experiences for users (e.g., gaming, online events). However, ensuring the user experience is still a challenge. Existing solutions are limited to measuring and estimating QoE at the user plane (e.g., VR player) or at the control plane, imposing unfeasible latency for different scenarios (5G networks and beyond). In this work, we propose QoEyes, an in-network QoE estimation based on the use of Inter-Packet-Gap (IPG) in programmable devices. Our results show that the IPG measured on the data plane is strongly linked to QoE, yielding an accurate data plane QoE estimate.

Recent advances in VR technology have created new user experiences (e.g., online events, gaming). However, ensuring the user experience is still a challenge. Mostly because Quality of Experience (QoE) measurement is limited to the user or control plane, causing high latencies for different scenarios (e.g., 5G networks and beyond). To address this challenge, we present QoEyes, an in-network QoE estimation technique based on Inter-Packet-Gap (IPG) measured in programmable devices. Our results show that a strong estimate of the user’s QoE can be provided by measuring the IPG on the data plane. Additionally, in this demonstration, we show this QoE estimate and other related metrics in real time, using a Grafana dashboard running in our monitoring server.