EDBT 2026 Demo / reviewers in the wild / expert
Dingyang Zou
dblp:335/2700
· DBLP profile ↗
4ranked-venue papers
3as first author
4since 2021 · last 2026
0000-0003-2749-420XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author · 4 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | EMSTrans: An Efficient Hardware Accelerator for Transformer With Multi-Level Sparsity Awareness
Dingyang Zou, Baichen Chen, Qiye Ding, Zhongfeng Wang 0001 |
IEEE Trans. Circuits Syst. I Regul. Pap. | 1 |
| 2025 | LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog GenerationabstractAdvancements in AI have increased the demand for specialized AI accelerators, with design for general matrix multiplication (GEMM) module being crucial but time-consuming. While large language models (LLMs) show promise for automating GEMM design, challenges arise from GEMM's vast design space and performance requirements. Existing LLM-based frameworks for RTL code generation often lack flexibility and performance awareness. To overcome the challenges, we propose LLM4GV, a multi-agent LLM-based framework that integrates hardware optimization techniques (HOTs) and performance modeling, improving correctness and performance of the generated code over prior works. Dingyang Zou, Gaoche Zhang, Kairui Sun, Zhe Wen, Zhongfeng Wang 0001 |
DATE | 1 |
| 2025 | ADCIM: scalable construction of approximate digital compute-in-memory MACRO for energy-efficient attention computation
Xu Zhang 0040, Dingyang Zou, Zhongfeng Wang 0001 |
J. Syst. Archit. | 3 |
| 2025 | An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN AcceleratorsabstractDue to the demand for high energy efficiency in deep neural network (DNN) accelerators, computing-in-memory (CIM) is becoming increasingly popular in recent years. However, current CIM designs suffer from high latency and insufficient flexibility. To address the issues, this brief proposes a Booth-multiplication-based CIM macro (BCIM) with modified Booth encoding and partial product (PP) generation method specially designed for CIM architecture. In addition, a methodology is presented for designing precision-reconfigurable digital CIM macros. We also optimize the precision-reconfigurable shift adder in the macro based on the cutting down carry connection method. The design attains a performance of 2048 GOPS and a peak energy efficiency of 79.15 TOPS/W in the signed INT4 mode at a frequency of 500 MHz. Dingyang Zou, Gaoche Zhang, Xu Zhang 0040, Zhongfeng Wang 0001 |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |