This paper presents a 915 MHz ultra-low-power (ULP) receiver based on a single-path third-harmonic mixing (SPTHM) architecture. Unlike conventional multi-path sub-harmonic receivers that require precise multi-phase local oscillators (LOs), this work simplifies the receiver to a single-mixer path architecture by jointly optimizing the LO harmonic order and duty cycle. The receiver is driven by a 10%-duty-cycle LO operating at one-third of the carrier frequency ($f_{\mathrm {c}}$). Compared to the typical 50%-duty-cycle LO in the SPTHM configuration, the proposed receiver improves the conversion gain by 12.1 dB and noise figure (NF) by 5.2 dB. The architecture also exhibits a front-end NF variation of less than 1 dB across the 3%-13% LO duty-cycle range, thereby relaxing constraints on pulse generation. To facilitate ULP channel selection, a comparison-skipped frequency-locked loop (FLL) is used, consuming just$5~\mu $W. A high-Q IF amplifier with an improved active inductor load is incorporated to enhance in-band interference rejection, achieving 31 dB signal-to-interference ratio (SIR) at 5 MHz offset. Fabricated in a 65 nm CMOS, the receiver achieves a sensitivity of −86 dBm at 250 kbps data rate with a$39.4~\mu $W power consumption, including an on-chip LO. It indicates a competitive figure-of-merit (FoM) of 184 dB within a compact active area of 0.16 mm2.

This paper presents a 915MHz multi-channel receiver for ultra-low-power (ULP) applications. A sub-passive third-harmonic mixer is proposed to improve the front-end conversion performance at the ULP budget. Driven by the local oscillator (LO) that operates at one-third of the RF carrier frequency with a duty cycle of about 10%, the proposed mixer improves the front-end’s noise figure (NF) to 15dB while reducing the LO power consumption by three times. The mixer also alleviates the requirement for LO phase accuracy. With the LO duty cycle ranging from 4% to 14%, the variation of the mixer performance is less than 10%, which allows a simple pulse generation approach without a precise duty cycle control circuit, thereby saving power consumption. A low-power frequency-locked loop (FLL) with a 196kHz tuning step facilitates channel selection. Additionally, a high-Q intermediate-frequency (IF) amplifier with an active inductor is used to suppress in-band interference and noise bandwidth. Implemented in a 65nm CMOS process and based on post-simulation results, the receiver achieves a sensitivity of −88dBm while consuming 40µW at a 250kb/s data rate. The receiver also performs an improved figure-of-merit (FoM) of 186dB with 26dB interference tolerance and a compact active area of 0.16mm2.

This paper presents a 915MHz bit-level duty-cycled (BLDC) wake-up receiver (WuRX) designed for ultra-low-power Internet-of-Things (IoT) systems. Utilizing an envelope-tracking (ET) mixer, the WuRX generates a phase-following (PF) local oscillator (LO) from the incoming radio-frequency (RF) signals. The recovered PF LO has a low duty cycle of about 10% and aligns the peak and valley voltages of the RF signal. As a result, the on-off keying data is accurately downconverted to the baseband with improved gain. Moreover, the high-speed sampling capability of the ET mixer allows the receiver’s front-end to operate at a low duty cycle of 0.024%, significantly lower than other mixer-based BLDC WuRXs. Dynamic baseband amplifiers with pre-charging and auto-zeroing abilities are employed to save area and reduce power consumption. Fabricated in a 65nm CMOS process, the proposed BLDC WuRX achieves a sensitivity of −73.2dBm at a 1kbps data rate, consuming only 97nW and occupying an ultra-low-area of 0.036mm2.

This paper presents a reference double-sampling phase-locked loop (RDSPLL) that integrates frequency multiplication and octa-phase clock generation into a single system, significantly reducing power consumption. A differential ring oscillator (DRO) is employed to generate octa-phase clocks with high phase accuracy. The reference double-sampling technique extends the loop bandwidth, effectively suppressing phase noise from the ring oscillator and thereby reducing jitter. To achieve accurate and efficient phase error detection, we proposed a novel offset-compensated hybrid phase detector (OCH-PD), featuring an offset calibration and a comparator-ADC hybrid quantizer. The offset calibration utilizes the CDAC to dynamically compensate for the mismatch in double-sampling, improving jitter and spur performance. The hybrid quantizer supports dynamic mode switching based on different locking states: during the coarse frequency locking phase, it operates in the ADC mode to accelerate the locking process; once a stable lock is achieved, it switches to the comparator mode to enable low-power, high-speed quantization. Fabricated in a 65-nm CMOS process, the prototype achieves 674 fs RMS jitter at 2.4 GHz while consuming only 3.43 mW, resulting in a$\text {FOM}_{\text {Jitter-N}}$of -251.9 dB. With offset calibration, the reference spur at 100 MHz is suppressed from -56 dBc to -80 dBc, and the jitter is reduced from 1.42 ps to 674 fs. The locking time improves from$10.5~{\mu }$s to$1.6~{\mu }$s using the hybrid quantizer. The eight-phase accuracy remains better than 1° over the frequency range of 2-2.8 GHz.