Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. Afterwards, we analyze how VCO gain mismatch and offset among oscillators can affect clock jitter robustness. Also, in-band noise degradation due to out-of-band signal interferers is described.

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250$\mu$W occupying 0.095$\text{mm}^2$in 130 nm CMOS.

This paper introduces a unique asynchronous digital version of the widely recognized LIF neuron model, which is commonly used in spiking neural networks. This proposed circuit provides a technologically scalable alternative to conventional analog implementations. Despite utilizing digital logic, the neuron circuit employs internal variable representations that are rate-encoded as spike trains. This approach simplifies the internal circuitry by eliminating the need for arithmetic circuits and minimizes power consumption, achieving a figure of merit of 310 fJ/SOP. The programmability of the parameters, combined with these features, facilitates the use of off-chip gradient learning techniques without performance degradation due to PVT and mismatch variations during deployment.

This paper introduces a new CMOS implementation of a spiking Leaky Integrate-and-Fire (LIF) neuron. The circuit does not require any analog circuit block such as comparators or current sources thanks to the use of a ring-oscillator as an integrator and a phase delay detector as threshold logic. The circuit admits both excitatory and inhibitory input spiking signals whose pulse width does not affect the computation. Instead of powering the ring oscillators from a power supply, the input spikes charge a capacitor bank which powers the ring oscillator. The paper describes the operation of the neuron analytically for the input integration and the membrane voltage decay. Also, a circuit-level simulation in 65nm CMOS technology has been performed, achieving a power efficiency of < 40fJ/spike.