This paper proposes GRIPT, a novel graph attention-based inductive methodology that enables a fast and accurate average power estimation of synthesized ASIC Design from RTL simulation, bypassing gate-level simulation. The proposed GRIPT methodology with features-aided attention mechanism-based inductive Graph Neural Network (GNN) model propagates the input wires’ toggle rates acquired from the RTL SAIF file through the circuit. We examine the proposed GRIPT methodology’s versatility by testing circuits across technology nodes and foundries like TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm while training exclusively on the TSMC 65nm technology node. We introduce unseen and untrained logic cells to test the transferability of the proposed GRIPT model in toggle rate prediction across technology nodes. We evaluate the scalability of the proposed GRIPT by testing circuits of considerable size, like circuit trigonometry from OpenCores, and circuits arbiter, multiplier, div, log2, sin, square and sqrt from the EPFL benchmark suite, without training them. The proposed GRIPT surpasses the state-of-the-art GRANNITE model in predicting the unseen and untrained logic cell’s toggle rates to justify the proposed GRIPT’s transferability for designs across technology nodes to achieve an average improvement of 6.74%, 5.53%, 8.93%, 6.88% and 7.22%, respectively. To demonstrate versatility and scalability, the proposed GRIPT methodology outperforms the commercial RTL power estimation tool and GRANNITE in estimating the average power of circuits spanning TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, with a mean improvement of 23.42%, 16.59%, 16.35%, 27.16%, and 28.87%; 2.01%, 0.97%, 0.98%, 1.6% and 2.72%, respectively. The proposed GRIPT is 12.57X and 1.1X faster, with an average inference throughput (number of cycles inferred per second) of 1384.6 Hz compared to the commercial gate-level power estimation tool and GRANNITE, respectively.

This paper proposes an inductive Graph Neural Network (GNN) based methodology for accurate and fast average power estimation of logic-synthesized and RTL-simulated ASIC Design, eliminating gate-level simulation. With the novel variation of inductive GNN architecture, the proposed model propagates the input wires’ toggle rates acquired from RTL simulation through the synthesized design. We only train the proposed model on circuits synthesized from TSMC 65nm technology node but test on the circuits synthesized across TSMC 65nm, 40nm, 90nm, 130nm and GF 40nm technology nodes. We test the inductivity of the proposed model to predict the output wires’ toggle rates of unseen and untrained logic cells of the designs. We compute the proposed methodology’s average power inference throughput (number of cycles inferred per second) for speed comparison. The proposed model does better than state-of-the-art architecture GRANNITE to predict the unseen and untrained logic cell’s toggle rates of the designs across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes, showing an average improvement of 6.67%, 8.49%, 9.26%, 7.47% and 6.36%, respectively. The proposed methodology is more accurate than the commercial RTL average power estimation tool and GRANNITE in estimating the average power of circuits across TSMC 65nm, 40nm, 90nm, 130nm, and GF 40nm technology nodes by achieving a mean improvement of 24.94%, 16.77%, 17.65%, 29.72%, and 32.84%; 2.75%, 1.1%, 1.81%, 2.59% and 4.49%; respectively. The proposed methodology is 11.07X faster, with an average inference throughput of 1.218kHz, than the commercial gate-level average power estimation tool.