Nowadays, warpage effect is becoming one of the main concerns in the manufacture of 2.5-D/3-D IC packages. Numerical simulation of warpage in the design stage by the finite element method (FEM) is required for manufacturability and reliability optimization. 2.5-D/3-D IC packages are generally composed of laminated thin plates with high aspect ratios and complex in-plane material boundaries, leading to intrinsic difficulties in obtaining high-quality hexahedral meshes essential for fast convergence and high-quality results. In this paper, we propose a novel meshing algorithm for efficient generation of sweep hexahedral meshes towards complex 2.5-D/3-D structures. On the basis of the sweep mesh, we utilize a modified 2-D layerwise plate theory to further improve the convergence of the solver. Compared with Ansys Workbench, our meshing algorithm can either reduce the meshing time (74.7× to 221×) and the number of mesh nodes (5.26× to 18.4×), or improve the mesh quality (3.45× to 9.75×) and reduce convergence time of the solver (1.48× to 4.50×), with < 0.5% errors. A 3.75× to 12.6× reduction in convergence time is further achieved with the proposed 2-D layerwise plate theory compared to the 3-D formulation, while maintaining the errors within 3%.

The post-exposure bake (PEB) process is a critical step in semiconductor lithography, directly impacting resist profile accuracy and circuit pattern fidelity. Precise modeling of PEB is essential for controlling photoacid diffusion and inhibitor reactions. In this paper, we introduce SDM-PEB, an advanced modeling framework designed to enhance the accuracy of PEB simulations by capturing both intra-layer spatial dependencies and inter-layer depthwise interactions. Leveraging a unique hierarchical feature extractor with overlapped patch merging and efficient self-attention, our approach effectively captures both coarse and fine features at multiple scales. The spatial-depthwise Mamba-based attention unit, centered on a customized selective scan and structured state space model, efficiently captures spatial and depthwise dependencies, enabling precise 3D PEB simulation. Additionally, a PEB focal loss and differential depth divergence regularization term improve the sensitivity to both spatial and depthwise variations, addressing inherent data imbalances in 3D PEB simulations. Our framework is validated with commercial rigorous model, and experimental results demonstrate that the SDM-PEB outperforms previous methods in accuracy and efficiency.

Thermomechanical stress induced by through-silicon vias (TSVs) plays an important role in the performance and reliability analysis of 2.5D/3D ICs. While the finite element method (FEM) adopted by commercial software can provide accurate simulation results, it is very time-and memory-consuming for large-scale analysis. Over the past decade, the linear superposition method has been utilized to perform fast thermal stress estimations of TSV arrays, but it suffers from a lack of accuracy. In this paper, we propose MORE-Stress, a novel strict numerical algorithm for efficient thermal stress simulation of TSV arrays based on model order reduction. Experimental results demonstrate that our algorithm can realize a 153–504 x reduction in computational time and a 39-115x reduction in memory usage compared with the commercial software ANSYS, with negligible errors less than 1%. Our algorithm is as efficient as the linear superposition method, with an order of magnitude smaller errors and fast convergence.

With the rise of 3-D integration technology, the back-end-of-line (BEOL) interconnects start to play an important role in thermal analysis, as they inevitably occupy the main thermal dissipation path of the active devices in 3-D ICs. High-resolution full-chip thermal resistance extraction of BEOL interconnects is thus needed to obtain accurate temperatures of local hotspots, which renders rigorous numerical simulation based extraction methods unaffordable. Several analytical models have been proposed for efficient full-chip thermal resistance extraction of BEOL interconnects, but they are very inaccurate due to the inability to consider the detailed via connectivity. In this paper, we propose a novel analytical model based on the resistor network theory and the Woodbury formula. Our model takes the detailed via connectivity into consideration and achieves a 3.4× improvement in accuracy compared with the previous work, with negligible time overhead. Owing to the accuracy improvement in the extracted thermal resistances, we reduce the absolute percentage error of the maximum temperature predicted by further thermal analysis of a 3-D IC based on the extracted thermal resistances from 5.2% to 1.8%, compared with the previous work.

The surge in consumer electronics is catalyzing the evolution of 2.5D integrated circuits (2.5D-IC). As these systems expand in scale and integrate more chiplets, the significance of chiplet design tools, particularly automatic chiplet placement, is increasingly apparent. Yet, previous studies did not sufficiently consider the distinctive features of chiplets, encountering challenges related to low quality of wire-length and poor scalability. Moreover, the pronounced high temperatures in 2.5D-ICs have not been thoroughly addressed, indicating a lack of thermal-aware design exploration. In response, this paper presents ATPlace2.5D, an analytical thermal-aware chiplet placement framework for large-scale 2.5D-ICs. It can deliver solutions that balance wirelength and temperature, residing on the optimal Pareto frontier, in collaboration with an innovative, physics-based compact thermal model. Experimental results show that AT-Place2.5D can handle more than 60 chiplets in minutes, and outperforms TAP-2.5D in both maximum temperature and total wire-length by 5% and 42% in thermal-aware placement, with a 23× acceleration. This advancement holds promise for promoting the maturity and widespread application of 2.5D-ICs.

Microstrip transmission line (MTL) appears extensively in microwave integrated circuits (MIC). To sufficiently analyze and synthesize the MTL, we propose MTL-Designer that can design the electrical and geometrical parameters of an MTL given performance specifications. We construct a deep generative model to generate initial solutions, and a surrogate model to predict the characteristics, optimize the solutions, and select from them. We further propose an adaptive sampling algorithm to speedup training. Our flow can generate 1000 feasible solutions within ∼0.6 s, realizing > 99.8% accuracy given various design specifications for two common MTL systems, exhibiting its strong potential for MIC design.

Post Exposure Baking (PEB) has been widely utilized in advanced lithography. PEB simulation is critical in the lithography simulation flow, as it bridges the optical simulation result and the final developed profile in the photoresist. The process of PEB can be described by coupled partial differential equations (PDE) and corresponding boundary and initial conditions. Recent years have witnessed growing presence of machine learning algorithms in lithography simulation, while PEB simulation is often ignored or treated with compact models, considering the huge cost of solving PDEs exactly. In this work, based on the observation of the physical essence of PEB, we propose DeePEB: a neural PDE Solver for PEB simulation. This model is capable of predicting the PEB latent image with high accuracy and >100 × acceleration (compared to the commercial rigorous simulation tool), paving the way for efficient and accurate photoresist modeling in lithography simulation and layout optimization.