Demo Data from EDBT 2026 / reviewers in the wild / expert
Jérôme Fereyre
dblp:336/1558
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2024
0009-0004-1519-7333ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Theory of computation · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 91% Hardware accelerators and domain-specific architectures · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic |
0.8 | 1 | 2024 | Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024 |
Processor architecture and microarchitecture
instruction set architecture |
0.8 | 1 | 2024 | Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024 |
Processor architecture and microarchitecture › instruction set architecture › ISA extension
RISC-V ISA extension |
0.8 | 1 | 2024 | Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024 |
Hardware accelerators and domain-specific architectures
scientific computing accelerator |
0.2 | 1 | 2024 | Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024 |
Methods — techniques the papers use, named apart from their topics
rounding mode support · 0.8hardware-assisted prefetching · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point ComputationabstractA key concern in the field of scientific computation is the convergence of numerical solvers when applied to large problems. The numerical workarounds used to improve convergence are often problem specific, time consuming and require skilled numerical analysts. An alternative is to simply increase the working precision of the computation, but this is difficult due to the lack of efficient hardware support for extended precision. We proposeXvpfloat, a RISC-V ISA extension for dynamically variable and extended precision computation, a hardware implementation and a full software stack. Our architecture provides a comprehensive implementation of this ISA, with up to 512 bits of significand, including full support for common rounding modes and heterogeneous precision arithmetic operations. The memory subsystem handles IEEE 754 extendable formats, and features specialized indexed loads and stores with hardware-assisted prefetching. This processor can either operate standalone or as an accelerator for a general purpose host. We demonstrate that the number of solver iterations can be reduced up to 5× and, for certain, difficult problems, convergence is only possible with very high precision (≥384 bits). This accelerator provides a new approach to accelerate large scale scientific computing. Eric Guthmuller, César Fuguet Tortolero, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand |
IEEE Trans. Computers | 4 |
| 2022 | Accelerating Variants of the Conjugate Gradient with the Variable Precision ProcessorabstractLinear algebra kernels such as linear solvers, eigen-solvers are the actual working engine underneath many scientific applications. The growing scale of these applications has led researchers to rely on high-precision computing for improving their efficiency and their stability. In this work, we investigate the impact of arbitrary extended precision on multiple variants of the Conjugate Gradient method (CG). We show how our VRP processor improves the convergence and the efficiency of these kernels. We also illustrate how our set of tools (library, software environment) enables to migrate legacy applications in a fast and intuitive way while preserving high-performance. We observe up to an 8X improvements on kernel iteration count, and up to a 40 % improvement on latency. Nevertheless, the main benefit is the stability gained with the precision. It makes it possible to resolve larger and ill-conditioned systems without costly compensating techniques. Yves Durand, Eric Guthmuller, César Fuguet Tortolero, Jérôme Fereyre, Andrea Bocco, Riccardo Alidori |
ARITH | 4 |