Demo Data from EDBT 2026 / reviewers in the wild / expert
Chaithanya Naik Mude
dblp:336/4225
· DBLP profile ↗
4ranked-venue papers
2as first author
4since 2021 · last 2025
0009-0002-0531-3551ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Security and privacy · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Emerging computing paradigms · 78% Hardware accelerators and domain-specific architectures · 22% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Theoretical computer science
1 paper |
Quantum computing and quantum information · 100% |
Topics — the 8 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms
quantum computer architecture |
1.8 | 3 | 2025 | Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025 Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023 Crosstalk-induced Side Channel Threats in Multi-Tenant NISQ Computers · NDSS 2025 |
Emerging computing paradigms › quantum computing and quantum information › quantum measurement
superconducting qubit readout |
1.5 | 2 | 2025 | Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025 Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023 |
Hardware security and side channels
side-channel attack |
0.9 | 1 | 2025 | Crosstalk-induced Side Channel Threats in Multi-Tenant NISQ Computers · NDSS 2025 |
Emerging computing paradigms
quantum computing |
0.9 | 1 | 2025 | Accurate Leakage Speculation for Quantum Error Correction · MICRO 2025 |
Emerging computing paradigms › quantum computer architecture
quantum error correction |
0.9 | 1 | 2025 | Accurate Leakage Speculation for Quantum Error Correction · MICRO 2025 |
Quantum computing and quantum information
quantum error correction |
0.9 | 1 | 2025 | Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout · DAC 2025 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.7 | 1 | 2023 | Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures · ISCA 2023 |
Emerging computing paradigms › quantum computer architecture
fault-tolerant quantum computing |
0.3 | 1 | 2025 | Accurate Leakage Speculation for Quantum Error Correction · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
neural network · 1.7matched filter · 1.7crosstalk analysis · 1.7FPGA · 1.7syndrome classification · 0.9error propagation graph · 0.9machine learning · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Efficient and Scalable Architectures for Multi-level Superconducting Qubit ReadoutabstractRealizing the full potential of quantum computing requires large-scale quantum computers capable of running quantum error correction (QEC) to mitigate hardware errors and maintain quantum data coherence. While quantum computers operate within a two-level computational subspace, many processor modalities are inherently multi-level systems. This leads to occasional leakage into energy levels outside the computational subspace, complicating error detection and undermining QEC protocols. The problem is particularly severe in engineered qubit devices like superconducting transmons, a leading technology for fault-tolerant quantum computing. Addressing this challenge requires effective multi-level quantum system readout to identify and mitigate leakage errors. We propose a scalable, high-fidelity three-level readout that reduces FPGA resource usage by $60 \times$ compared to the baseline while reducing readout time by $20 \%$, enabling faster leakage detection. By employing matched filters to detect relaxation and excitation error patterns and integrating a modular lightweight neural network to correct crosstalk errors, the protocol significantly reduces hardware complexity, achieving a $100 \times$ reduction in neural network size. Our design supports efficient, real-time implementation on off-the-shelf FPGAs, delivering a $6.6 \%$ relative improvement in readout accuracy over the baseline. This innovation enables faster leakage mitigation, enhances QEC reliability, and accelerates the path toward faulttolerant quantum computing. Chaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit S. Tannu |
DAC | 1 |
| 2025 | Accurate Leakage Speculation for Quantum Error CorrectionabstractQuantum Error Correction (QEC) protects qubits against bit-and phase-flip errors in the |0⟩ /|1⟩ subspace, but physical qubits can also leak into higher energy levels (e.g., |2⟩).Leakage is especially harmful, as it corrupts all subsequent syndrome measurements and can spread to neighboring qubits.Detecting leakage on data qubits is particularly challenging, since they are never measured directly during QEC cycles.Prior work, such as eraser [43], addresses this by inferring leakage from syndrome patterns using a fixed heuristic.However, this approach often misclassifies benign syndromes, triggering excessive leakage-reduction circuits (LRCs).Because LRCs are themselves noisy and slow, these false triggers lengthen QEC cycles and inflate logical error rates.We propose gladiator, a general and adaptable leakage speculation framework that works across surface code, color code, and qLDPC codes.Offline, gladiator builds a code-aware errorpropagation graph calibrated to device data.Online, it classifies each syndrome in a few nanoseconds and schedules LRC only when the observed pattern is provably leakage-dominated.This precise speculation eliminates up to 3× (and on average 2×) unnecessary LRCs, shortens QEC cycles, and suppresses false positives at their source.Evaluated on standard fault-tolerant benchmarks, gladiator delivers 1.7×-3.9×speedups and 16% reduction in logical error rate, advancing the efficiency of fault-tolerant quantum computing. Chaithanya Naik Mude, Swamit S. Tannu |
MICRO | 1 |
| 2025 | Crosstalk-induced Side Channel Threats in Multi-Tenant NISQ Computers
Navnil Choudhury, Chaithanya Naik Mude, Sanjay Das, Preetham Chandra Tikkireddi, Swamit S. Tannu, Kanad Basu |
NDSS | 2 |
| 2023 | Scaling Qubit Readout with Hardware Efficient Machine Learning ArchitecturesabstractReading a qubit is a fundamental operation in quantum computing. It translates quantum information into classical information enabling subsequent classification to assign the qubit states '0' or '1'. Unfortunately, qubit readout is one of the most error-prone and slowest operations on a superconducting quantum processor. On state-of-the-art superconducting quantum processors, readout errors can range from 1--10%. These errors occur for various reasons - crosstalk, spontaneous state transitions, and excitation caused by the readout pulse. The error-prone nature of readout has resulted in significant research to design better discriminators to achieve higher qubit-readout accuracies. High readout accuracy is essential for enabling high fidelity for near-term noisy quantum computers and error-corrected quantum computers of the future. Satvik Maurya, Chaithanya Naik Mude, William D. Oliver, Benjamin Lienhard, Swamit S. Tannu |
ISCA | 2 |