Single-event upsets (SEUs) pose a critical reliability threat in advanced automotive and space electronics. While existing SEU-tolerant latch designs, such as those based on C-elements and unique modules, often fail to meet the stringent space radiation standards (linear energy transfer (LET)$= 60~\text {MeV} \cdot \text {cm}^{2}$/mg) at advanced fin field-effect transistor (FinFET) technology nodes, triple modular redundancy (TMR) achieves sufficient tolerance but incurs significant overhead. To address these limitations, this brief introduces DN-FF, a novel detection-node flip-flop (DN-FF) architecture that leverages reduced node spacing in modern processes for complete SEU immunity with significantly reduced overhead compared to TMR. Incorporating strategically placed detection nodes (DNs) and a dedicated detection circuit (DC), DN-FF achieves robust radiation-hardness while significantly reducing physical area, delay, and power consumption compared to traditional TMR-based solutions. The experimental results demonstrate that DN-FF reduces area by 8.2%, delay by 18.4%, and power by 15.9%, delivering a 37% improvement in the overall area–delay–power quality (ADPQ) metric. These advantages make DN-FF a compact, high-performance, and reliable solution for demanding automotive and aerospace applications.

In safety-critical applications such as biomedical and automotive electronics, soft errors induced by radiation particles pose a significant reliability concern. This paper presents a novel Filtering Buffer-based D Flip-Flop (FB-DFF) designed to enhance radiation hardening while minimizing area and timing overheads. The FB-DFF integrates a Filtering Buffer (FB) and an Auto Delay Element (ADE) to effectively filter out transient errors and ensure the correct input signal is latched. The Single-Master Dual-Slaves (SMDS) architecture further prevents error propagation to the output. Experimental results demonstrate that FB-DFF can resist radiation particles below 77 LET, providing full protection against both Single Event Transient (SET) and Single Event Upset (SEU). Compared to existing designs, FB-DFF reduces area overhead by 44% and timing overhead by 144% at the chip level, making it a highly efficient solution for radiation-hardened applications. The proposed FB-DFF offers a balanced trade-off between radiation hardening capability, area, and timing performance, making it suitable for integration into various safety-critical systems.

Single-Event Double-Node Upsets (SEDUs) increasingly compromise the integrity of storage cells like latches or flip-flops, especially as technology scales down to sub-65nm nodes. Traditional RHBD (Radiation-Hardened by Design) strategies, such as DICE and TMR, crafted to counter Single-Event Node Upset (SEU), are proving to be inadequate to SEDU. Consequently, recent research suggests the use of expanded areas to shield circuits from SEDUs, yet this often results in disproportional overhead. In response, the LESER methodology emerged as an effective measure, introducing minimal redundancy while still guaranteeing full SEDU resilience. However, having mitigated SEDUs across different latches within ASAP7 (a predictive process), LESER calls for further improvement in three pivotal issues: (1) spacing impact, (2) dummy gates, and (3) device configuration. Thus, LESER-2 has been developed, targeting these three challenges in latches designed with two industrial process nodes. LESER-2 presents a dual-level architecture, encompassing both device and circuit strata. At the device level, LESER-2 replaces the virtual process model card with industrial ones, significantly enhancing simulation accuracy concerning heavy ion impacts on transistors. Additionally, circuit-level layout modification within LESER-2 are meticulously calibrated to mitigate SEDUs in vulnerable node pairs. Empirical tests validate the LESER-2 modifications applied to latches under two industrial process nodes, accomplishing a 100% rate of soft error prevention while incurring an average area overhead of 16.5%, effectively resolving the three aforementioned issues.

Many existing soft-error-tolerant flip-flop designs (e.g., MDAD-FF, SETU-TOFF, SEDR-FF) apply delayed latching to mitigate strikes of radiation particles. However, according to AEC-Q100 (Grade 1), automotive electronics are permitted to operate at temperatures between −40°C to 125°C, resulting in two reliability issues: (1) protection failure and (2) timing degradation. At −40°C, these rad-hard FF designs are capable of providing a worst-case delay of only 113 ps, ineffective in protecting against 77-LET particles (which require 200 ps in 45 nm process). At 125°C, however, the performance of these FF designs may degrade to 386 ps, resulting in more timing violations. Therefore, RAV-FF is proposed to address these two issues by incorporating a MOSFET capacitance (MCAP) to generate sufficient delay to delay clock and a current-control transistor (CC) to stabilize delay at different temperature corners. Experimental results indicate that RAV-FF provides effective soft-error protection in the temperature range of −40°C to 125°C by ensuring a delay of at least 200 ps with only 3% variation.

Single-event-induced soft errors are serious issues in advanced nano-scale technology, causing malfunctions in systems. As the size of technology node decreases to sub-65nm with closer transistor spacing, single-event double-node upsets (SEDU) occur more frequently than single-event upsets (SEU). Previous studies handled SEDU by incorporating protection mechanisms in cell designs or modifying the physical layout. However, they have massive area overhead and SEDU cannot be fully prevented. In this paper, we propose a LESER framework to reconstruct the latch design, achieving 100% SEDU tolerance. Based on the concept of engineering change order (ECO), LESER contains a two-level analysis process to prevent SEDU with minimum modification on layout, including 1) device level and 2) circuit level. The device level extracts the current source model by TCAD simulation and the circuit level reconstructs the layout with scanning process, double-node injection test, and layout modification approach. Experiments show that the reconstructed design can achieve a 100% soft error protection rate with the costs of an increment of 6.4% in area, 1% in timing and power penalty. The results indicate that LESER can fully prevent SEDU by reconstructing the latch with minimum performance penalties.

A single-event double-node upset (SEDU) may appear to result in an erroneous state of the storage element due to the scalability of transistor features. Therefore, SEDU must be well addressed from the perspective of circuit reliability, especially for safety-critical electronics. Some previous studies claimed to protect against SEDUs in 65-nm process technologies, but were not thoroughly verified. To better understand the technology-scaling impact, we re-examine SEDU in different advanced technologies (including 7-nm finFET, 45-nm bulk CMOS, and 65-nm bulk CMOS). An integrated multi-level framework is developed with the current-source modeling derived from the device-level TCAD simulation, combined with voltage calculation derived from the circuit-level SPICE simulation. To adequately capture the probability of errors occurring in the latch design under all possible scenarios, this paper also considers a variety of environmental factors, such as strike angles, temperature variation, and technology nodes. Also, three classical latch designs (i.e., TMR, DICE, and HLR) have been implemented in different technologies and well calibrated for experiments. According to experiment results, it is evident that SEDU is highly dependent on both the physical layout of the design as well as its design style. DICE is found to be the most susceptible to SEDU in all three manufacturing technologies, whereas TMR and HLR can be immune to SEDU in the 45-nm and 65-nm technologies due to a lack of sufficient charge to upset more than two nodes. It is, therefore, essential to consider both the physical layout and the manufacturing technology employed for ensuring the robustness of a radiation-hardened design against particle strikes.