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Kiyong Kwon

dblp:337/4957 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Hardware accelerators and domain-specific architectures · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
processing-in-memory
0.612022
Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests · IEEE Trans. Parallel Distributed Syst. 2022
Memory systems › processing-in-memory
processing-using-DRAM
0.612022
Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests · IEEE Trans. Parallel Distributed Syst. 2022
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator
0.212022
Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests · IEEE Trans. Parallel Distributed Syst. 2022
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.212022
Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests · IEEE Trans. Parallel Distributed Syst. 2022

Methods — techniques the papers use, named apart from their topics

DMA offloading · 0.6
YearPublicationVenuePosition
2022 Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests
abstract
The Deep Neural Network (DNN), Recurrent Neural Network (RNN) applications, rapidly becoming attractive to the market, process a large amount of low-locality data; thus, the memory bandwidth limits their peak performance. Therefore, many data centers actively adapt high-bandwidth memory like HBM2/HBM2E to resolve the problem. However, this approach would not provide a complete solution since it still transfers the data from the memory to the computing unit. Thus, processing-in-memory (PIM), which performs the computation inside memory, has attracted attention. However, most previous methods require the modification or the extension of core pipelines and memory system components like memory controllers, making the practical implementation of PIM very challenging and expensive in development. In this article, we propose a Silent-PIM that performs the PIM computation with standard DRAM memory requests; thus, requiring no hardware modifications and allowing the PIM memory device to perform the computation while servicing non-PIM applications' memory requests. We can achieve our design goal by preserving the standard memory request behaviors and satisfying the DRAM standard timing requirements. In addition, using standard memory requests makes it possible to use DMA as a PIM's offloading engine, resulting in processing the PIM memory requests fast and making a core perform other tasks. We compared the performance of three Long Short-Term Memory models (LSTM) kernels on real platforms, such as the Silent-PIM modeled on the FPGA, GPU, and CPU. For (p ×512) ×(512 ×2048) matrix multiplication with a batch size p varying from 1 to 128, the Silent-PIM performed up to 16.9x and 24.6x faster than GPU and CPU, respectively, p=1, which was the case without having any data reuse. At p=128, the highest data reuse case, the GPU performance was the highest, but the PIM performance was still higher than the CPU execution. Similarly, at (p ×2048) element-wise multiplication and addition, where there was no data reuse, the Silent-PIM always achieved higher than both CPU and GPU. It also showed that when the PIM's EDP performance was superior to the others in all the cases having no data reuse.
Won Jun Lee, Yoonah Paik, Kiyong Kwon, Seokyoung Kim 0001, Il Park 0001, Seon Wook Kim
IEEE Trans. Parallel Distributed Syst.4