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Sean Brock

dblp:339/0275 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0003-9822-9283ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › layout verification
design rule checking
0.712023
DRDebug: Automated Design Rule Debugging · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Electronic design automation
physical design
0.712023
DRDebug: Automated Design Rule Debugging · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023

Methods — techniques the papers use, named apart from their topics

rule language processing · 0.7random layout generation · 0.7
YearPublicationVenuePosition
2023 DRDebug: Automated Design Rule Debugging
abstract
Design rule checking (DRC) is an important step in the physical design flow that checks if a design meets the manufacturing constraints or design rules imposed by the process technology. It allows the foundry to ensure high acceptable manufacturing yield. Design rule verification is one of the most challenging steps because of the sheer size of the rule decks and the lack of standardization among these design rule manuals (DRMs). One way of efficiently discovering missed rule checks is by comparing the rule deck with that of another mature or well-established process. In this work, we develop two complementary techniques for comparing process design rule decks and automatically establishing a one-to-one correspondence between rules from two different process design kits (PDKs). The first approach, random layout generation (RLG), creates random layouts of different shapes and sizes. The generated layout is checked using both rule decks. The rules are then matched based on the violations generated. The second approach, based on rule language processing (RLP), matches rules based on the similarity between rule commands. Rules are directly matched based on the layer names and keywords present in the DRC commands. The two approaches are complementary and together they can correctly match more than 80% of the rules in two DRMs.
Irina Alam, Tianmu Li, Sean Brock, Puneet Gupta 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3