The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality [1] , [2] . Recent studies tried to predict timing errors using machine learning (ML), while considering some workload characteristics [3] , [4] , [5] . However, successfully training such models is challenging, since traditionally acquired samples are insufficient, especially in operating regions where timing errors occur rarely.

This paper showcases the novel application of Deep-Learning (DL) in the development of accurate microarchitecture and workload-aware timing error models and investigates methods such as sparsification for reducing their complexity, while maintaining high accuracy. Our study shows that DL can help increase the accuracy and true positive rate (TPR) of workload-aware models for a pipelined floating-point core compared to existing models. In addition, we demonstrate that removing up to 40% of the total neurons has minimal impact on the accuracy and overall predictive performance (up to 2.2%) of our DL-based timing error models, while significantly reducing the computational complexity. In fact, the complexity of the sparse model is approximately 2× smaller than the dense one.

Nanometer circuits are becoming increasingly prone to timing errors due to worsening parametric variations and operation close to voltage and frequency limits. Such errors threaten the system functionality and make circuits increasingly vulnerable to fault injection attacks, thus escalating the need to accurately predict and avoid them. Recent studies focus on modelling these errors by exploiting various supervised Machine Learning (ML)-based techniques. However, such efforts have not yet explored Neural Network (NN) methods that could improve accuracy, while being more easily scalable to complex, deep-pipelined architectures. This is the first study to explore the application of NN models on the accurate prediction of timing errors while considering various microarchitecture and workload parameters. To enable this study, we utilized stochastic search-based techniques to generate error-prone microarchitecture-aware samples, even in operating regions where samples are limited, the large number of which is an essential requirement in deep learning modelling. Our novel framework combines post-layout dynamic timing analysis and genetic algorithms, considering the data-dependent path sensitization and instruction execution history. The generated samples are used to train and evaluate various NN models for timing error prediction under multiple operating conditions. To evaluate the high efficacy of the NN models, we tested them on 6 applications with more than 8.5M instruction sequences. Evaluation results show over 99.8% predictive accuracy, combined with up to a 121.35% increase (on average) of the true positive rate in real test data compared to prior studies.

Nanometer circuits are increasingly prone to timing errors, escalating the need forfault injectionframeworks to accurately evaluate their impact on applications. In this paper, we propose ARETE, a novel cross-layer, fault-injection framework that combines dynamic-binary instrumentation with machine learning-guided dynamic-timing analysis. ARETE enables accurate fault-injection into any application by estimating the location of the injecting errors via dynamic-timing analysis. To accelerate fault-injection, we develop a novel, data-aware, machine learning-based mechanism that dynamically pre-selects the error-prone instructions and limits the application of the costly dynamic-timing analysis only to them. To evaluate ARETE's accuracy, our fully automated toolflow is configured to support fault-injection based on detailed post-layout gate-level simulations as well as via existing workload-agnostic error models. Our results for various workloads, including an autonomous-driving library, show that the location and time of injected errors performed by ARETE, is 89.9% consistent with fault-injection based on full gate-level simulation. On average, ARETE executes 84.6× faster than gate-level simulation and at a cost of 3.4% loss in the program output quality estimation. When compared to the existing statistical fault-injection tools that are based on workload-agnostic error models, ARETE improves the accuracy of fault-injection rate and output quality estimation by 143.9% and 40.4% on average, respectively.

The adoption of aggressively down-scaled voltages along with worsening process variations, render nanometer devices prone to timing errors that threaten system functionality. The increased vulnerability of nanometer circuits to these errors attracted recent efforts in the development of timing error prediction models using machine learning (ML) methods. However, the majority of such models may be inaccurate, since they either neglect important microarchitecture properties and workload-dependent parameters, affecting timing error manifestation, or are constrained to limited operating areas. In this paper, we propose microarchitecture- and workload-aware ML models for timing error prediction that jointly consider various instruction types as well as all in-flight instructions in a pipeline. Our proposed models are able to predict the exact time and location (i.e., cycle, instruction and bit position) of timing errors with over 98% accuracy across multiple, critical operating regions. To circumvent the increased model complexity due to the considered features, we apply for the first time significance-driven approximations. Evaluation results for various workloads and voltage reduction levels show that our significance-driven precision scaling improves the models’ inference time up to 4.66×, with less than 4% accuracy loss. Finally, we use the proposed model to accurately and realistically inject timing errors during the evaluation of application resiliency. When compared to prior timing error evaluation frameworks that rely on workload-agnostic models, our framework improves the output quality estimation up to 82.6%.