This paper proposes a Heterogeneous Last Level Cache Architecture with Readless Hierarchical Tag and Dynamic-LRU Policy (HARD), designed to enhance system performance and reliability by leveraging the complementary advantages of Static Random-Access Memory (SRAM) and Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM). In the Data RAM, by integrating SOT-MRAM, HARD increases cache capacity under the same area constraints, effectively alleviating performance bottlenecks caused by memory access latency. To better manage the designed Data RAM, we introduce a Dynamic Least Recently Used (Dynamic-LRU) policy, which dynamically adjusts data placement based on access patterns, storing access-intensive data in the SRAM region while migrating access-sparse data to the SOT-MRAM region. This approach not only ensures the performance of the last level cache in high-speed access scenarios but also optimizes storage resource utilization and significantly reduces write pressure on SOT-MRAM. Furthermore, in the Tag RAM, to address the read disturbance issue of SOT-MRAM, we introduce a readless hierarchical tag structure. This structure also employs a heterogeneous design of SRAM and SOT-MRAM, reducing unnecessary matching operations through hierarchical architecture and readless comparison schemes, thereby lowering energy consumption and improving the reliability of the Tag RAM. Experimental results demonstrate that HARD excels in complex data access scenarios, achieving a 40.6× improvement in Mean Time To Failure (MTTF) for the Tag RAM and a 6.3% reduction in miss rate attributed to the increased cache capacity under the same area budget for the Data RAM, offering an efficient and scalable cache solution for high-performance computer architectures.

Analog in-memory-computing (AIMC) is adopted extensively in non-volatile memory for multibit multiply-and-accumulate (MAC) operation. However, the low-on/off-ratio feature of magnetic tunnel junction (MTJ) impedes a high-performance AIMC macro based on spin transfer torque magnetic random access memory (STT-MRAM). Secondly, because of the uncertainty feature of a mixed-signal system under process and voltage variation, a calibration support is indispensable. Moreover, the incompatibility between a nonlinear analog signal and a linear digital signal hinders accurate computation and calibration support. To overcome these challenges, this work proposes a STT-MRAM-AIMC macro featuring: 1) a 2-level-differential cell array and a linear computing scheme with a calibration support in analog domain; 2) an analog-digital-conversion (ADC) system, including a slew-rate-independent voltage-to-time converter (SRIVTC) scheme and a self-triggered time-to-MAC value converter (STTMC) scheme; 3) a compact layout design for high area efficiency. Finally, an average accuracy of 95.44% is obtained under the TT&0.9V corner. By using the calibration strategy, the average accuracy of 97.8% and 88.6% are obtained under FF&0.945V and SS&0.855V separately, with over 30% enhancement. Furthermore, a 1.64~21.18 times area FoM than state of the art is obtained. An energy efficiency of 87.2~312.4 TOPS/W is obtained.

Today, machine vision experiences large latency due to big data processing, which is a barrier to time-critical applications. To address this issue, in-sensor computing was presented in the past. Here, we present a scheme of computing in a magnetic tunneling junction (MTJ) sensor array for proof-of-principle. Using the MTJ sensor array, the functions of artificial neural network (ANN) classifiers and autoencoders were verified. The time for correct classification of one picture was less than$9~\mu \text{s}$. The power consumed in the sensor array can be decreased according to the square law without affecting the results. Our work shows universal circuits and algorithms to compute in resistance-style ANN image sensors with promising energy efficiency.