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Demo Data from EDBT 2026 / reviewers in the wild / expert

Yuhan Diao

dblp:339/8697 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0000-0003-4146-1666ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 56% Reconfigurable computing and FPGAs · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA-accelerated simulation		 0.712023
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023
Electronic design automation › hardware verification and test
hardware verification		 0.712023
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023
Electronic design automation › hardware verification and test › functional verification
FPGA verification		 0.212023
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023

Methods — techniques the papers use, named apart from their topics

reference model checking · 0.7FPGA acceleration · 0.7
YearPublicationVenuePosition
2023 ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
abstract
Verification typically consumes the majority of the time in the hardware development cycle. Primarily this is because multiple iterations to debug hardware using software simulation is extremely time-consuming. While FPGAs can be utilised to accelerate the simulation, existing methods either provide limited visibility of design details, or are expensive to check against a reference model dynamically at the system level.
Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao
 FPGA3