Demo Data from EDBT 2026 / reviewers in the wild / expert
Shuoxiang Xu
dblp:339/8990
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2025
0000-0003-3185-3463ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 79% Reconfigurable computing and FPGAs · 21% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
1.5 | 2 | 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration · FPGA 2025 ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023 |
Electronic design automation › hardware verification and test › hardware verification
high-level synthesis verification |
0.9 | 1 | 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration · FPGA 2025 |
Electronic design automation › hardware verification and test › functional verification
RTL verification |
0.9 | 1 | 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration · FPGA 2025 |
Reconfigurable computing and FPGAs
FPGA-accelerated simulation |
0.7 | 1 | 2023 | ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.3 | 1 | 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration · FPGA 2025 |
Electronic design automation › hardware verification and test › functional verification
FPGA verification |
0.2 | 1 | 2023 | ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration · FPGA 2023 |
Methods — techniques the papers use, named apart from their topics
FPGA acceleration · 1.5C/RTL co-simulation · 0.9reference model checking · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA AccelerationabstractHigh-Level Synthesis (HLS) enables software engineers to create intricate digital circuit designs using high-level languages like C/C++. While HLS tools can perform functional verification using C/C++ simulation, it is harder to verify that the generated RTL is also correct. This problem is exacerbated for designs which include HLS-generated IPs, such as PCIe or DDR interfaces, or hand-written RTL. While it is possible to perform cycle-accurate verification using C/RTL co-simulation, conventional methods are both slow and typically only focus on unit-level verification which can make it harder to identify the root cause of a bug. Shuoxiang Xu, Zijian Jiang, David Boland, Yungang Bao, Kan Shi |
FPGA | 1 |
| 2023 | ENCORE: Efficient Architecture Verification Framework with FPGA AccelerationabstractVerification typically consumes the majority of the time in the hardware development cycle. Primarily this is because multiple iterations to debug hardware using software simulation is extremely time-consuming. While FPGAs can be utilised to accelerate the simulation, existing methods either provide limited visibility of design details, or are expensive to check against a reference model dynamically at the system level. Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao |
FPGA | 2 |