This article presents the design and implementation of a fully differential Successive Approximation Register (SAR) analog-to-digital converter (ADC) in 65 nm UMC technology, specifically targeting biomedical applications where area efficiency is a critical requirement. The design prioritizes achieving clean and precise first-order Noise Shaping (NS) by integrating a switched-capacitor-based integrator with our proposed C-2C ladder DAC topology, which is instrumental in significantly reducing area consumption. Noise performance is optimized by carefully correlating the capacitances of the integrator and DAC, ensuring precision and stability. To achieve robust operation, the design incorporates a process, voltage, and temperature (PVT)-resilient methodology for all system blocks, providing consistent performance and reliability under challenging conditions and variations in fabrication. The implemented prototype achieves an area efficiency of 0.058 mm 2 , 10.37 ENOB over a 20 kHz Bandwidth, and operates at a 1 MHz sampling rate with a power consumption of 448 μ W . • This research exhibits for the first time, the NS SAR incorporating a C2C DAC. • The design specifications target biomedical applications, with good trade-offs. • The proposed design improves Integration for the NS-SAR. • The design aims for resilience to Process, Voltage, and Temperature Variations. • The experimental results in the Integrated Circuit prototype show the benefits.

This paper presents a novel quarter-rate Clock Data Recovery (CDR) topology, wherein the phase-tracking loop is implemented using eight Phase Interpolators (PIs). Each PI provides 15 discrete steps between every 45° phase increment, enabling the accurate detection of edge or data samples during plesiochronous operation. The PI is digitally controlled by a circuit topology that facilitates both coarse and fine phase adjustments, thereby enhancing linearity and minimizing Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) errors.Phase selection within the CDR is governed by a digital majority vote scheme and a four-bit digital counter. The design and layout were executed using 65nm CMOS technology, targeting a data rate of 10Gb/s and an operating frequency of 2.5GHz for the PI. This setup achieves an angular resolution of approximately 2.81° per code, with a standard delay of 3.125ps. The proposed system was validated through simultaneous post-layout simulations, incorporating the PI, CML2CMOS buffers, and CML latches. Additionally, Verilog-AMS simulations were used to model jitter generation within a pseudo-random bit sequence (PRBS) and to design the corresponding digital logic operations.

In this article, motor imagery Electro-Encephalographic (EEG) signals for Brain-Computer interfaces (BCI) are processed under a weak signal detection (WSD) paradigm, with the goal to improve the low EEG Signal to Noise Ratio (SNR). Based on our previous results, Stochastic resonance (SR) is proposed, as a WSD method on EEG signals, for the first time. This novel methodology takes advantage of noise transitions on a non-linear, bi-stable, double well system. These transitions are synchronized with brain oscillations embedded in the EEG signal, achieving the desired brain waves enhancement. More over, our methodology modifies the bistable well separation and depth modulation on the Duffing system, having as target point the maximum SNR hence, recovering most of the input waveform shape. Dataset from the international BCI competition IV was used in this research, with an estimated SNR of -24dB. After stochastic resonance processing, the resulting signal enhancement on the desired μ - β band was observed, with an output SNR of 1.31dB during motor imagery and 1.41dB on resting states. In order to demonstrate the signal processing methodology applicability, a single EEG trial is reported from 17 channels processed. Also, for comparative purposes, dyadic wavelet transform (DWT) was applied to the same EEG signal. The results exhibit comparable, or even a better, signal enhancement with SR methodology than DWT processing.