The Internet of Things (IoT) and smart devices are currently being deployed in systems such as autonomous vehicles and medical monitoring devices. The introduction of IoT devices into these systems enables network connectivity for data transfer, cloud support, and more, but can also lead to malware injection. Since many IoT devices operate in remote environments, it is also difficult to protect them from physical tampering. Conventional protection approaches rely on software. However, these can be circumvented by the moving target nature of malware or through hardware attacks. Alternatively, insertion of the internal monitoring circuits into IoT chips requires a design trade-off, balancing the requirements of the monitoring circuit and the main circuit. A very promising approach to detecting anomalous behavior in the IoT and other embedded systems is side-channel analysis. To date, however, this can be performed only before deployment due to the cost and size of side-channel setups (e.g., and oscilloscopes, probes) or by internal performance counters. Here, we introduce an external monitoring printed circuit board (PCB) named RASC to provide r emote a ccess to s ide- c hannels. RASC reduces the complete side-channel analysis system into two small PCBs (2 \( \times \) 2 cm), providing the ability to monitor power and electromagnetic (EM) traces of the target device. Additionally, RASC can transmit data and/or alerts of anomalous activities detected to a remote host through Bluetooth. To demonstrate RASCs capabilities, we extract keys from encryption modules such as AES implemented on Arduino and FPGA boards. To illustrate RASC’s defensive capabilities, we also use it to perform malware detection. RASC’s success in power analysis is comparable to an oscilloscope/probe setup but is lightweight and two orders of magnitude cheaper.

Power side-channel (PSC) attacks received significant attention over the past two decades due to their effectiveness in breaking mathematically strong cryptographic implementations. However, most existing PSC assessment frameworks apply only to post-silicon implementations; this is unfavorable to the industry due to the lack of flexibility in fixing the design and the high cost/time penalty incurred in redoing the entire design cycle. This article presents the register transfer level (RTL)-power analysis tool (PAT) framework to perform a technology-independent PSC assessment of cryptographic (pre- and post-quantum) hardware at the RTL stage. Performing assessment at the RTL gives designers the utmost flexibility to quickly apply the countermeasures locally. RTL-PAT can also serve as a front-end sign-off framework for PSC leakage, allowing a designer to make changes in the early design stage, which would otherwise be difficult/time-consuming to perform in subsequent design stages. Furthermore, RTL-PAT can analyze both FPGA and ASIC design flows for standalone IPs and SoCs. In this article, we present the efficacy of RTL-PAT on several cryptographic implementations. The results are presented for standalone IPs, which include different AES implementations (Galois field, lookup table, pipelined, and threshold implementation) andPRESENTcipher. We also analyze a large-scale SoC, which includes the post-quantum SABER implementation and AES. The results show that the framework effectively identifies the leaky modules and validates the efficacy of PSC countermeasures implemented in the RTL. The obtained RTL-PAT assessment results are validated with the post-silicon$t$-statistics assessment as well.

Power side-channel attacks (SCAs) exploit leakage from cryptographic implementations to recover secrets in a non-invasive manner. Existing power side-channel assessment techniques mostly focus on post-silicon stages, suffering from the extremely low flexibility in changing designs to address identified leakages. In this paper, we propose a framework called PSC-TG which supports side-channel leakage assessment at the earliest stage of design cycle, i.e., RTL, allowing the maximum flexibility for countermeasure deployment. The assessment starts with RTL information flow tracking to identify the most sensitive variables according to pre-defined SCA-aware properties. Then, formal assertions are generated based on these variables and the presumed attack model to derive the corresponding test patterns. Next, the sidechannel vulnerability (SCV) metric is calculated using the estimated power with as low as two patterns to quantify the first-order sidechannel leakage. Besides, PSC-TG can give pass/fail indication for masked implementations at higher orders with t-test. We experimentally evaluate the leakage of multiple non-protected benchmarks at RTL, and validate with gate-level and FPGA results. Also, the t-test results of the masked Simon implementation are consistent with the post-silicon findings.

With the rise of Internet of Things (IoT), devices such as smartphones, embedded medical devices, smart home appliances as well as traditional computing platforms such as personal computers and servers have been increasingly targeted with a variety of cyber attacks. Due to limited hardware resources for embedded devices and difficulty in wide-coverage and on-time software updates, software-only cyber defense techniques, such as traditional anti-virus and malware detectors, do not offer a silver-bullet solution. Hardware-based security monitoring and protection techniques, therefore, have gained significant attention. Monitoring devices using side channel leakage information, e.g. power supply variation and electromagnetic (EM) radiation, is a promising avenue that promotes multiple directions in security and trust applications. In this paper, we provide a taxonomy of hardware-based monitoring techniques against different cyber and hardware attacks, highlight the potentials and unique challenges, and display how power-based side-channel instruction-level monitoring can offer suitable solutions to prevailing embedded device security issues. Further, we delineate approaches for future research directions.

Power side-channel attacks (SCAs) have been proven to be effective at extracting secret keys from hardware implementations of cryptographic algorithms. Ideally, the power side-channel leakage (PSCL) of hardware designs of a cryptographic algorithm should be evaluated as early as the pre-silicon stage (e.g., gate level). However, there has been little effort in developing computer-aided design (CAD) tools to accomplish this. In this article, we propose an automated CAD framework called SCRIPT to evaluate information leakage through side-channel analysis. SCRIPT starts by defining the underlying properties of the hardware implementation that can be exploited by side-channel attacks. It then utilizes information flow tracking (IFT) to identify registers that exhibit those properties and, therefore, leak information through the side-channel. Here, we develop an IFT-based side-channel vulnerability metric ( SCV ) that is utilized by SCRIPT for PSCL assessment. SCV is conceptually similar to the traditionally used signal-to-noise ratio (SNR) metric. However, unlike SNR, which requires thousands of traces from silicon measurements, SCRIPT utilizes formal methods to generate SCV-guided patterns/plaintexts, allowing us to derive SCV using only a few patterns (ideally as low as two) at gate level. SCV estimates PSCL vulnerability at pre-silicon stage based on the number of plaintexts required to attain a specific SCA success rate. The integration of IFT and pattern generation makes SCRIPT efficient, accurate, and generic to be applied to any hardware design. We validate the efficacy of the SCRIPT framework by demonstrating that it can effectively and accurately determine SCA success rates for different AES designs at pre-silicon stage. SCRIPT is orders of magnitude more efficient than traditional pre-silicon PSCL assessment (SNR-based), with an average evaluation time of 15 minutes; whereas, traditional PSCL assessment at pre-silicon stage would require more than a month. We also analyze the PSCL characteristic of the multiplication unit of RISC processor using SCRIPT to demonstrate SCRIPT’s applicability.

Quantum phenomena cannot be predicted by the uncertainty principle. As a quantum phenomenon, radioactive decay has been used as an entropy source to generate random numbers. In this article, we present the design and development of an innovative quantum entropy chip (QEC) that produces analog random pulses when emitted alpha particles resulted from radioactive isotope (americium-241) decay hit the sensor. The analog pulse generated by a QEC can be digitized into random numbers by an entropy extractor. The QEC provides security foundation for device authentication as well as a quantum random number generator (QRNG), especially suited for the Internet of Things (IoT) devices due to its small size. We have successfully designed and fabricated the QEC as a wafer for supporting a system-on-chip (SoC) Internet Protocol (IP) so that the QEC can be embedded into a microcontroller unit (MCU) or central processing unit (CPU). In addition, we built a stochastic model to estimate the entropy of the quantum source and evaluated statistical randomness and robustness against temperature, voltage variations, aging effects, and physical attacks. Finally, we demonstrate various applications using the QEC such as side-channel-resistant primitives and device authentication.

Random number generators play a pivotal role in generating security primitives, e.g., encryption keys, nonces, initial vectors, and random masking for side-channel countermeasures. A quantum entropy source based on radioactive isotope decay can be exploited to generate random numbers with sufficient entropy. If a deterministic random bit generator (DRBG) is combined for post-processing, throughput of the quantum random number generator (QRNG) can be improved. However, general DRBGs are susceptible to side-channel attacks. In this paper, we propose a framework called SCR-QRNG framework, which offers Side-Channel Resistant primitives using QRNG. The QRNG provides sources of randomness for modulating the clock frequency of a DRBG to obfuscate side-channel leakages, and to generate unbiased random numbers for security primitives. The QRNG has robustness against power side-channel attacks and is in compliance with NIST SP 800-22/90B and BSI AIS 31. We fabricate a quantum entropy chip, and implement a PCB module for a random frequency clock generator and a side-channel resistant QRNG on an FPGA.

Power side-channel attacks (SCAs) have become a major concern to the security community due to their noninvasive feature, low-cost, and effectiveness in extracting secret information from hardware implementation of cryto algorithms. Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAs during its design and validation stages. Currently, however, there is little known effort in evaluating the vulnerability of a hardware to SCAs at early design stage. In this paper, we propose, for the first time, an automated framework, named RTL-PSC, for power side-channel leakage assessment of hardware crypto designs at register-transfer level (RTL) with built-in evaluation metrics. RTL-PSC first estimates power profile of a hardware design using functional simulation at RTL. Then it utilizes the evaluation metrics, comprising of KL divergence metric and the success rate (SR) metric based on maximum likelihood estimation to perform power side-channel leakage (PSC) vulnerability assessment at RTL. We analyze Galois-Field (GF) and Look-up Table (LUT) based AES designs using RTL-PSC and validate its effectiveness and accuracy through both gate-level simulation and FPGA results. RTL-PSC is also capable of identifying blocks* inside the design that contribute the most to the PSC vulnerability which can be used for efficient countermeasure implementation.

Modern embedded computing devices are vulnerable against malware and software piracy due to insufficient security scrutiny and the complications of continuous patching. To detect malicious activity as well as protecting the integrity of executable software, it is necessary to monitor the operation of such devices. In this paper, we propose a disassembler based on power-based side-channel to analyze the real-time operation of embedded systems at instruction-level granularity. The proposed disassembler obtains templates from an original device (e.g., IoT home security system, smart thermostat, etc.) and utilizes machine learning algorithms to uniquely identify instructions executed on the device. The feature selection using Kullback-Leibler (KL) divergence and the dimensional reduction using PCA in the time-frequency domain are proposed to increase the identification accuracy. Moreover, a hierarchical classification framework is proposed to reduce the computational complexity associated with large instruction sets. In addition, covariate shifts caused by different environmental measurements and device-to-device variations are minimized by our covariate shift adaptation technique. We implement this disassembler on an AVR 8-bit microcontroller. Experimental results demonstrate that our proposed disassembler can recognize test instructions including register names with a success rate no lower than 99.03% with quadratic discriminant analysis (QDA).