Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down design methodology, which not only goes through code construction and optimization, but also hardware implementation to meet all the critical requirements, is presented. A two-step array dispersion algorithm is proposed to construct long LDPC codes with a small submatrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain better bit-error rate (BER) performance and lower error-floor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix leading to a proposed hybrid storage architecture, which has the advantages of better area efficiency and large enough data bandwidth for high decoding throughput. To be adopted for NAND flash applications, an (18900, 17010) LDPC code with a code-rate of 0.9 and submatrix size of 63 is constructed and the field-programmable gate array simulations show that the error floor is successfully suppressed down to BER of 10-12. An LDPC decoder using normalized min-sum variable-node-centric sequential scheduling decoding algorithm is implemented in UMC 90-nm CMOS process. The postlayout result shows that the proposed LDPC decoder can achieve a throughput of 1.58 Gb/s at six iterations with a gate count of 520k under a clock frequency of 166.6 MHz. It meets the throughput requirement of both NAND flash memories with Toggle double data rate 1.0 and open NAND flash interface 2.3 NAND interfaces.

As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.

This paper presents a non-binary LDPC decoder based on stochastic arithmetic. Although the previous stochastic works reduce the complexity of check node by transforming the convolution of the SPA algorithm to the finite field summation, the stochastic decoder still has a implementation bottleneck due to large storage introduced by the variable node process. Considering a balance between algorithm level and implementation level, we propose a shortened TFM architecture as well as its updating criterion. A compare-and-alter counter architecture is also proposed to avoid sorting among counters which decide the decoded codeword. With these features, the proposed (136, 68) fully-parallel stochastic NB-LDPC decoder over GF(32) implemented in UMC 90-nm can achieve 120 Mb/s throughput while operating under 455 MHz with 740 k gate counts which are only 10 % of the original TFM decoder.

The performance of LT code is highly related to the code length. A decoder is more likely to deplete degree-1 encoding symbols and terminate during early stage when the code length is short. In this work, we modify the robust Soliton distribution (RSD) and increase the degree-1 proportion. More degree-1 encoding symbols can be generated to relieve early decoding termination. The proportion of low degrees, except for degree-1, is also reduced. Therefore, receivers collect less encoding symbols carrying redundant information. In addition, Non-Repetitive (NR) encoding scheme is proposed to avoid producing repeated degree-1 encoding symbols. To improve video transmission quality, previous studies redesign LT codes to provide Unequal Error Protection (UEP) for different Scalable Video Coding (SVC) layers. Unlike those studies to modify the code structure, we integrate multiple NR encoders to achieve UEP ability. Experimental results show that our UEP scheme outperforms previous studies in terms of the PSNR.

Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.