Large-format single-photon avalanche diode (SPAD)-based direct time of flight (dToF) sensors are expected to be widely applied in future L5 full driving automation. However, the high-power in-pixel TDCs and the huge amount of data generated by multiframe histogram sampling impose limitations on the pixel format of SPAD-based dToF sensors. To tackle this challenge, we proposed the Computing-in-pixel Edge-aware Detection and Reconstruction (CEDAR) architecture. In this architecture, edge pixels are recognized by charge-domain convolution (CDC) computing, and noise pixels are eliminated by in-memory denoising (IMD). Only few TDCs in these edge pixels are activated, resulting in significant power and data savings. Afterward, the full-format image is reconstructed by a U-Net using the obtained depth information from these edge pixels. For the first time, we proposed a high-resolution 512 × 512 SPAD-based dToF sensor with a low power of 83.3 mW, a distance accuracy of 0.9 cm, and a frame rate of 60 fps. The high-resolution 3D image can be reconstructed by only 3.5% sparse edge pixels, achieving a PSNR of 35.2 dB. The CEDAR architecture can achieve 16× pixel format and image resolution improvement under the same constraint of power dissipation.

An algorithm to estimate jointly the symbol timing and carrier phase for continuous-phase modulation (CPM) is described. It is designed to optimize the steady-state performance of the CPM synchronizer and exhibits excellent performance, very close to the optimum maximum-likelihood estimate. The algorithm is simple and practical and may be employed with any CPM scheme. It is based on a signal space decomposition of the CPM signal in the Walsh signal space.

A simple receiver structure for any continuous phase modulation (CPM) scheme is introduced. Its front end is just the ordinary linear receiver followed by a subinterval sampler, eliminating the need for the standard analog matched filters. Its design is based on the decomposition of the CPM signal in the Walsh signal space. This brings the hardware requirement to a minimum, and near-optimum performance can be easily obtained.