Katsutoshi Kawakami

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1ranked-venue papers

0as first author

0since 2021 · last 2012

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Energy-efficient computing · 28% Processor architecture and microarchitecture · 22% Memory systems · 22%

Topics — the 6 heaviest of 6, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Processor architecture and microarchitecture › chip multiprocessor 3d chip multiprocessor	0.1	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012
Integrated circuit design 3d integration	0.1	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012
Memory systems › 3d-stacked memory stacked DRAM	0.1	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012
Energy-efficient computing thermal management	0.1	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012
Energy-efficient computing power management	0.0	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012
Parallel and multicore computing runtime optimization	0.0	1	2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints · DAC 2012

Methods — techniques the papers use, named apart from their topics

thermal modeling · 0.1runtime optimization policy · 0.1

Year	Publication	Venue	Position
2012	Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints abstract 3D multicore systems with stacked DRAM have the potential to boost system performance significantly; however, this performance increase may cause 3D systems to exceed the power budget or create thermal hot spots. This paper introduces a framework to model on-chip DRAM accesses and analyzes performance, power, and temperature tradeoffs of 3D systems. We propose a runtime optimization policy to maximize performance while maintaining power and thermal constraints. Our policy dynamically monitors workload behavior and selects among low-power and turbo operating modes accordingly. Experiments with multithreaded workloads demonstrate up to 49% energy efficiency improvements compared to existing thermal management policies. Katsutoshi Kawakami, Ayse K. Coskun	DAC	2