This study addresses the issue of blastomere cleavage timing, which is traditionally deemed the most important indicator in embryo quality assessment. We propose a novel quantization method for analyzing Time-lapse Incubator (TLI) images of embryos. This method incorporates five image classifiers, an instance segmentor, and the Expectation-Maximization (EM) algorithm to provide a cost-effective and reliable tool and to offer interpretable data for further research in the reproductive medicine field. The method is characterized in that the EM algorithm is employed to enhance the performance of classifiers and segmentor in fitting different patient data sources. The method enables (1) to identify the absolute cleavage timing of blastomere, i.e., tPNa, tPNf, t2, t3, t4, t8, t6, t7, and t8, (2) tracking the cleavage process of blastomere to highlight the irregular cleavage (IRC) patterns, (3) to quantitatively assess the symmetry degree of blastomere. Our method reduces the average time difference between Ground Truth and CTP to just 2.9 hours, a significant improvement over the 6.13 hours reported by Vitrolife™. Moreover, our method identifies up to eight cleavage time points, surpassing the six cleavage time points provided by Vitrolife™.

With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects on transistor and interconnect performance are well-studied, the interactions between power-delivery and thermal effects are not clear. As a result, power-delivery design without thermal consideration may cause soft-error, reliability degradation, and even premature chip failures. In this paper, we propose a thermal-aware power-delivery optimization algorithm. By simultaneously considering thermal and power integrity, we are able to achieve high power supply quality and thermal reliability. For a 58/spl times/72 mesh as shown in the experimental results, our algorithm shows that the lifetime of the optimized ground network is 9.5 years. Whereas the lifetime of the ground network generated by a traditional method is only 2 years without thermal concern.

Net weighting is a key technique in large scale timing driven placement, which plays a crucial role for deep submicron physical synthesis and timing closure. A popular way to assign net weight is based on the slack of the nets, trying to minimize the worst negative slack (WNS) for the entire circuit. While WNS is an important optimization metric, another figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points, is of equivalent importance to measure the overall timing closure result for highly complex modern ASIC and microprocessor designs. In this paper, we perform a comprehensive analysis of the slack and FOM sensitivities to the net weight, and propose a new net weighting scheme based on the slack and FOM sensitivities. Such sensitivity analysis implicitly takes potential physical synthesis effect into consideration. Experiment results on a set of industrial circuits are promising for both stand-alone timing driven placement and physical synthesis afterwards.

Recent studies show that the nonuniform thermal distribution on the substrate and interconnects has impact on the circuit reliability and performance. Hence three-dimensional (3-D) thermal analysis is crucial to analyze these effects. In this paper, we present and develop an efficient 3-D transient thermal simulator based on the alternating direction implicit (ADI) method for large scale temperature estimation problems. Our simulator, 3D Thermal-ADI, not only has a linear runtime and memory requirement, but also is unconditionally stable. Detailed analysis of the 3-D nonhomogeneous cases and boundary conditions for on-chip VLSI applications are introduced and presented. Extensive experimental results show that our algorithm is not only orders of magnitude faster than the traditional thermal simulation algorithms, but is also highly accurate and memory efficient. The temperature profile of steady state can be reached in few iterations. The software is avaiable on the web [1].

Due to the dramatic increase of clock frequency and integration density, power density and on-chip temperature in high-end very large scale integration (VLSI) circuits rise significantly. To ensure the timing correctness and the reliability of high-end VLSI design, efficient and accurate chip-level transient thermal simulations are of crucial importance. In this paper, we develop and present an efficient transient thermal-simulation algorithm based on the alternating-direction-implicit (ADI) method. Our algorithm, thermal-ADI, not only has a linear run time and memory requirement , but is also unconditionally stable, which ensures that time step is not limited by any stability requirement. Extensive experimental results show that our algorithm is not only orders of magnitude faster than the traditional thermal-simulation algorithms, but also highly accurate and efficient in memory usage.

Over the year, researchers have proposed the core based tree (CBT) and protocol independent multicast (PIM) protocols to route multicast data on the Internet. Such protocols need to locate the core of a group to have efficient multicast routing. In this paper, we propose a scalable distributed protocol that can be used to move the core to a near-optimal location for a dynamic multicast tree, and allow the core to migrate efficiently when the multicast tree is expanded or shrunk. In our protocol, it does not require knowledge of the complete network topology, and information of overall members is distributed among local agents; the core only maintains information of agents of the group. Also, only the agents participate in core selection. Therefore, the proposed protocol reduces the runtime overhead and message complexity while doing core migration.

Recent study shows that the nonuniform thermal distribution not only has an impact on the substrate but also interconnects. Hence, three-dimensional (3-D) thermal analysis is crucial to analyze these effects. In this paper, the authors present and develop an efficient 3-D transient thermal simulator based on the alternating direction implicit (ADI) method for temperature estimation in a 3-D environment. Their simulator, 3D Thermal-ADI, not only has a linear runtime and memory requirement, but also is unconditionally stable. Detailed analysis of the 3-D nonhomogeneous cases and boundary conditions for on-chip VLSI applications are introduced and presented. Extensive experimental results show that our algorithm is not only orders of magnitude faster than the traditional thermal simulation algorithms but also highly accurate and memory efficient. The temperature profile of steady state can also be reached in several iterations. This software will be released via the web for public usage.

Due to the dramatic increase of clock frequency and integration density, power density and on-chip temperature in high-end VLSI circuits rise significantly. To ensure the timing correctness and the reliability of high-end VLSI design, efficient and accurate chip-level transient thermal simulations are of crucial importance.