A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.

This VGA is designed for a GSM subsampling receiver. It operates at an IF frequency of 246MHz. The VGA provides a 60dB digitally controlled gain range in 2dB steps. The VGA is implemented in a 0.35/spl mu/m CMOS process. The current is 9mA@3V. The overall gain accuracy is less than 0.3dB. The noise figure at maximum gain is 8.7dB. The IIP3 is -4dBm at minimum gain.

Most class AB push-pull output buffers have been developed for supply voltages /spl ges/3.0 V. Recently developed class AB buffers, which operate at a voltage supply lower than 3.0 V, use sophisticated feedback circuits to control the quiescent current. In this paper, a simple class AB buffer is proposed. It can be used at 1.5 V power supply and has the capability to drive small resistive loads (<100 /spl Omega/). The circuit has been fabricated using a 1.2 /spl mu/ digital CMOS process. Experimental results demonstrate that the proposed circuit provides good control over the quiescent current. The standard deviation of the quiescent current is 17%. Combined with a floating gate input stage, a rail-to-rail input/output op amp has been fabricated and tested.

A nonlinear parameterizable macromodel for CMOS Operational Transconductance Amplifiers (OTAs) is presented. The macromodel captures the DC, AC and large signal features of the transistor level original circuit, thus modeling accurately its time domain and nonlinear performance. The main contribution of this work is to account for the bias-dependent transconductance nonlinearities in the circuit, by curve-fitting the desired output characteristics with n-dimensional polynomials. The model can also account for the nonlinear dependence of the circuit's characteristics on several design parameters. The applicability of the model is demonstrated by modeling the response of an OTA-C filter.

In this paper, we report on delay models for CMOS, BiCMOS, and BiNMOS inverters. A two-step iterative approach has been adopted to account for the slope of the input waveforms. The Alpha-Power Law model equations have been used for the short-channel MOSFET's. The effects of high collector current on the base transit time and the current gain are also included in the models of the bipolar transistors. The developed delay models are incorporated in a timing simulator to estimate the propagation delay of chains with mixed CMOS/BiCMOS/BiNMOS gates. The estimates of the simulator deviate from those of HSPICE by less than 10%, while it is faster than HSPICE by two orders of magnitudes. Hence, it can be used for identifying critical paths in VLSI systems.>