EDBT 2026 Demo / reviewers in the wild / expert
Arash Saifhashemi
dblp:34/1949
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 64% Energy-efficient computing · 31% Electronic design automation · 4% | |
| Theoretical computer science
1 paper |
Mathematical optimization · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
asynchronous circuit design |
0.3 | 2 | 2017 | Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction · DAC 2003 |
Energy-efficient computing › low-power design
power optimization |
0.3 | 1 | 2017 | Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Integrated circuit design › asynchronous circuit design
quasi delay insensitive circuits |
0.3 | 1 | 2017 | Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Mathematical optimization
integer programming |
0.1 | 1 | 2017 | Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2003 | Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction · DAC 2003 |
Methods — techniques the papers use, named apart from their topics
integer linear programming · 0.6heuristic algorithm · 0.6Verilog HDL · 0.0PLI · 0.0CSP · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Reconditioning: A Framework for Automatic Power Optimization of QDI CircuitsabstractThis paper introduces reconditioning: a novel systematic technique for reducing unnecessary power consumption of asynchronous gate-level netlists, which involves the optimal reordering of conditional communication and logic primitives. Our technique is applicable to asynchronous circuits with handshaking protocols that encode data and control together, in particular, quasi delay insensitive and 1-of-N handshaking circuits. Both an optimal integer linear program (ILP) and a fast heuristic algorithm are presented. We show that our ILP is feasible for moderate size circuits and our heuristic algorithm scales to much larger circuits, completing in seconds on circuits with tens of thousands of gates. Our experimental results show power improvement highly depends on the structure of the circuit but can often be above 26% with typically less than 5% area overhead. Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2015 | Logical equivalence checking of asynchronous circuits using commercial tools
Arash Saifhashemi, Hsin-Ho Huang, Priyanka Bhalerao, Peter A. Beerel |
DATE | 1 |
| 2005 | MILO: personal robot platformabstractRecent advances in mobile robotic technology has given rise to new types of robotic applications called personal robotics. The main feature of these applications is that they require low cost robots that involve assisting people in doing their everyday jobs such as providing personal assistance, commercial security, mobile tele-conferencing, tele-presence, home services, entertainment, and elderly care. In this paper we introduce a low cost and general purpose mobile robotic platform called MILO. It offers unique hardware and software features which make MILO suitable for a wide spectrum of personal robotic applications. MILO possesses PC architecture and runs on Windows XP. We have experimentally evaluated MILO's performance. Preliminary results show that MILO can be effectively used to develop personal robotic applications. Behnam Salemi, Jorge Reis, Arash Saifhashemi, Fred Nikgohar |
IROS | 3 |
| 2003 | Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstractionabstractIn this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions. Arash Saifhashemi, Hossein Pedram |
DAC | 1 |