Highly repetitive structures in IC, such as SRAM cells typically require extremely low failure ratio, making traditional Monte Carlo analysis extremely time consuming. Furthermore, the “curse of dimensionality” has become a major challenge for existing high-sigma yield analysis techniques. Thus, we propose a “sampling-training-substitution-verification” (STSV) yield analysis framework, which utilizes machine learning (ML) techniques to accelerate yield analysis in high-sigma and high-dimensional scenarios, effectively addresses the “curse of dimensionality.” In our framework, least absolute shrinkage and selection operator (Lasso) regression is adopted to substitute the mapping from process parameters to circuit performance, achieving high accuracy, and generalization. The model is adaptive for both low- and high-dimensional scenarios since the dimensional sparsity is achieved by$l1$regularization. In addition, important process parameters can be identified by sparse feature weights of the Lasso model, which is of assistance for yield optimization. Compared with existing yield analysis techniques, the Lasso-based STSV framework offers great saving in a simulation program with integrated circuit emphasis (SPICE) cost, is attractive in high-dimensional demands.