In this paper, we propose algorithms for presynthesis estimation of hardware cost of a streaming accelerator. Our proposed estimation method helps to accelerate the design-space-exploration phase by orders of magnitude by eliminating the need to perform logic and physical synthesis in each iteration. We present algorithms to perform early cost estimation of resources that are specific to a streaming accelerator, and we evaluate our techniques using an industrial tool flow and a set of streaming benchmarks. For the register-queue sizes, our estimations are in the range of 28%-9% of actual synthesis results on average, depending on the given resource constraints, while the datapath area estimations are within 14%. A typical estimation requires less than a minute, while generating the configuration bitstream of a streaming accelerator can take as much as 30 min according to our experiments. Considering several repetitions of the synthesis stage for the design space exploration, our estimation framework yields an order of magnitude speedup.

Recent advanced power optimizations deployed in commercial FPGAs, laid out a roadmap towards FPGA devices that can be integrated into ultra low power systems. In this article, we present a high-level design tool to support the process of mapping an application onto a FPGA device with dual supply voltages. Our main contribution in this paper is an algorithm, which creates voltage scaling ready clusters by utilizing the timing slack available in the designs. We propose to first create clusters of CLBs within a given CLB-level netlist. This clustering algorithm intends to group chains of CLBs possessing similar amounts of timing slack along their critical path together. Once these clusters are identified, they are placed onto respective V dd partitions on the device. We have evaluated different dual V dd fabrics and the potential gain in power consumption is explored. When a subset of the logic blocks on the device can be driven by low V dd levels (either with a dedicated low V dd supply or with a programmable selection between low and high V dd levels for these blocks) this affects placement and routing. As a result the maximum frequency of the designs may be affected. In order to evaluate the overall impact of creating voltage islands, we measured the Energy-Delay Product for our benchmark designs. We observed that the Energy-Delay product can be decreased by 26.9% when the placement of the designs into different voltage levels is guided by our clustering algorithm.

In this paper the authors propose a pre-synthesis register queue size estimation technique for an unscheduled streaming DFG (sDFG) for pipelined synthesis. Our estimation method first designates a minimum queue size to each communication edge of the sDFG based on the ALAP value of the source node and ASAP value of the sink node of that edge. Our aim is to further refine this initial minimum queue size estimation. Our main tool is based on the likelihood estimation that the source node may actually be producing data before its ALAP time, and likewise, the sink node may actually be consuming data after its ASAP time

In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-Vdd-dual-Vtrouting architecture to reduce interconnect power consumption by using two levels of Vddand Vt(Mondal and Memik, (2005))

One of the major challenges in automated synthesis of reconfigurable accelerators is to create efficient designs that conform to the resource capacity of the target device. This work concerns estimation of the hardware cost before actually attempting the synthesis of streaming accelerators on reconfigurable platforms. Specifically, our proposed framework tackles the problem of presynthesis estimation of data queuing cost, while incorporating the potential impact of resource constraints on the final implementation. We present a probabilistic push-and-pull approach for register queue size estimation of a streaming data flow graph. We evaluated our techniques using an industrial tool/low. For the register queue sizes our estimations are within the range of -14.4% to 12.4% on an average, for various resource constraints on a set of multimedia applications

Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power systems. With current technology scaling and integration trends timely and accurate detection of localized heating will be evermore important. In this work, we address the creation of a resource efficient sensor infrastructure for computing systems that are of regular nature, such as logic array-based computing platforms. We propose algorithms to embed thermal sensors into a regular structure to minimize the number of sensors and determine sensor locations required to maintain a given accuracy in temperature sensing for a given design. Our algorithms are tailored for minimal usage of thermal sensors to suit a variety of architectural conditions. For programmable logic arrays the highly application-specific usage of the hardware resources leads to unpredictable thermal profiles. As a result, post-manufacture instantiation of thermal sensors is desired, which in turn demands the use of native hardware resources, which can be scarce. We demonstrate that using our techniques the number of sensors required to monitor a set of hotspots is reduced by 75 % on an average, across different sizes of logic arrays for different hotspot distributions compared to a uniform distribution of sensors throughout the fabrics.

Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate the thermal behavior of general applications on fine-grain reconfigurable fabrics and we introduce the pre-mapping sensor insertion problem for thermal monitoring. Our study shows that on average the maximum temperature on the chip is 19.5degC higher than the ambient temperature for a transition density of 0.5 at the primary inputs. For fine-grain reconfigurable devices targeted for general applications it is difficult to predict the locations of potential hotspots a priori. However, programmability presents a unique opportunity for effective thermal monitoring. It would allow us to perform a thermal simulation on a given design first and obtain the locations of potential points of interest in a design. Then, in the pre-mapping stage the design can be updated with insertion of thermal sensors. Given a set of expected hot spots in a design we aim to determine the minimum number of sensors and their locations in order to monitor these locations with a given sensitivity requirement. Since the thermal sensors are implemented using unused CLBs on the fabric it is essential to use the logic resources efficiently. We propose an efficient algorithm to solve the sensor placement problem addressing this optimization goal

Efficient use of limited available resources on an FPGA remains a crucial problem for synthesizing pipelined designs. Resource sharing addresses this challenge. In this paper, we propose resource sharing techniques that can be incorporated into an automated synthesis flow to generate pipelined designs. Given a synthesized pipelined design, we create a direct relationship between available time slack on modules and the multiplexing overhead due to sharing. This flexibility is maximally exploited without violating any throughput constraints. We propose different techniques to address resource sharing problems of varying restrictions. Specifically, we propose an optimal algorithm for Constant-Slack Resource Sharing and a heuristic for the general Intra-Pipeline Stage Resource Sharing. On an average the demand on arithmetic functional units can be reduced by 39.5% for a set of benchmarks from the multimedia domain using our resource sharing technique.

Reconfigurable technologies have made remarkable progress in the last few years. However, due to the overhead of programmability along with improved system capabilities, power dissipation has become one of the major concerns for designers. Moreover, with the trends in technology scaling, overall leakage power consumption is increasing alarmingly. In this work, we propose a leakage power optimization technique using look-up tables (LUTs) for SRAM-based FPGAs. Analysis of a set of 20 MCNC benchmarks using 4-input LUTs show that on an average only 53% of these LUTs use all their inputs. Based on this observation, we shut down SRAM cells and certain transistors associated with the unused inputs by employing hierarchical look-up tables, which can yield LUTs with varying number of inputs within the same logic block. We effectively utilize a Vdd gating scheme to cut-off power supply to one half or three quarters of the original 4-input LUT, which in turn yields a 3-input LUT or a 2-input LUT from a 4-input LUT respectively. Our experiments show that for 180 nm technology logic block leakage power savings is 22.9% on an average for the set of 20 MCNC benchmarks. This saving will be even higher for technologies 90 nm and smaller.

FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.