UML and specialized profiles, such as MARTE, are established specification and modeling procedures in the system development process. While language-based system specification and resource modeling shortens the design cycle, the exploration of the design-space is time-consuming. Most expensive proves the generation of system models respectively the architectural alternatives for exploration. This work contributes a method that utilizes activity threads to reduce the effort, needed to build such a set. With this method, a group of system models, each representing one design alternative, can automatically be generated. Therefore, only one architecture model and one function model in combination with an activity thread is required. The proposed method is the first step towards automated comparison of the performance for design alternatives at an early stage in the development process.

In this papers we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict top-down Hardware/Software Codesign paradigm using stepwise refinement techniques. Starting from a performance, evaluation on the data-flow level using the OCAPI system, we partition the simulated high-level data-flow description into hardware and software modules. The hardware parts, described in Handel-C, are compiled and mapped to Xilinx Virtex 2000E FPGAs, and the software is executed on a PC processor that hosts the Virtex boards. Hardware/Software interfacing, and communication between processor and FPGA is established via the PCI bus by shared memory DMA transfers. This paper presents the methodology and illustrates the method with an example of a channel coder.

Article Free Access Share on Java driven codesign and prototyping of networked embedded systems Authors: Josef Fleischmann Technical University of Munich, Inst. of Electronic Design Automation, D-80290 Munich, Germany Technical University of Munich, Inst. of Electronic Design Automation, D-80290 Munich, GermanyView Profile , Klaus Buchenrieder Siemens AG, Corporate Technology, D-81730 Munich, Germany Siemens AG, Corporate Technology, D-81730 Munich, GermanyView Profile , Rainer Kress Siemens AG, Corporate Technology, D-81730 Munich, Germany Siemens AG, Corporate Technology, D-81730 Munich, GermanyView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 794–797https://doi.org/10.1145/309847.310068Published:01 June 1999Publication History 7citation356DownloadsMetricsTotal Citations7Total Downloads356Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In the design of embedded hardware/software systems, exploration and synthesis of different design alternatives and co-verification of specific implementations are the most demanding tasks. Networked embedded systems pose a new challenge to existing design methodologies as novel requirements like adaptivity and runtime-reconfigurability arise. In this paper; we introduce a co-design environment based on the Java language which supports specification, co-synthesis and prototype execution for dynamically reconfigurable hardware/software systems.

The paper presents a scalable architecture for multi-threaded Java applications. Threads enable modeling of concurrent behavior in a more or less natural way. Thus threads give a migration path to multi-processor machines. The proposed architecture consists of multiple application-specific processing elements, each able to execute a single thread at one time. The architecture is evaluated by implementing a portable and scalable Java machine onto an FPGA board for demonstration.