An individual-user-optimized, adaptive beamforming method for a mobile satellite system (MSS) is presented. The system creates a `beam for each user', referred to as `user beam'. The user beam is optimized based either on known user locations or the waveforms received from all cochannel users. The system operates in an environment of significant frequency reuse among the cochannel users. Knowledge of user locations is transferred to the S-BSS (Satellite Base Station Subsystem) by the return link or is derived at the S-BSS from estimation of the spatial signature of the return link signals and knowledge of pilot signals in the return link waveform. The user beam maximizes the signal-to-interference-and-noise ratio (SINR) relative to the desired user, both in the forward and return links. The optimization process considers the spatial distribution of all cochannel users in the footprint of the satellite. The user beam adapts to the user's location and co-channel interference environment. By simulation, the performance of the beamforming system is compared with an existing, fixed beamforming system, represented by a major GEO MSS covering the Continental United States (CONUS) and Canada. The simulation results show that user-optimized adaptive beamforming offers significant capacity advantages over the legacy beamforming, measured by aggregate system throughput.

It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. An important design constraint in such architectures is that the FIFO buffers connecting the processing elements (in a pipelined fashion) should not overflow and the playout buffer should never underflow. To meet these constraints, an usual design practice is to increase the initial playout delay after which the output device starts reading from the playout buffer. Although implementing this technique is straightforward and involves only the the computation of an appropriate playout delay, it suffers from the downside of a large playout buffer being required. In this paper, instead of associating the playout delay solely with the output device, we propose to redistribute this delay among all the processing elements running the various tasks of the multimedia application. We show that this delay redistribution technique can signficantly reduce (up to 70%) the total on-chip memory required.

This paper describes the architecture, functionality, and design of NX-2700, a digital television and media processor chip from Philips Semiconductors. The NX-2700 is the second generation of an architectural family of programmable multimedia processors targeted at the digital television (DTV) markets, including the United States Advanced Television Systems Committee (ATSC) DTV-standard-based applications. The chip not only supports all of the 18 ATSC formats from standard-definition to wide-angle, high-definition video, but has also the power to handle high-definition television (HDTV) video and audio source decoding (high-level MPEG-5 AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. NX-2700 is a programmable processor with a very powerful, general-purpose very long instruction word (VLIW) central processing unit (CPU) core that implements many nontrivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units) and high-performance buses, facilitates concurrent processing of audio, video, graphics, and communication-data.

This paper describes the architecture, functionality, and design of a Talisman-compatible multimedia processor (TM-PC) from Philips Semiconductors. "Talisman" is the code name of a new graphics and multimedia hardware architecture (from Microsoft Corp.) that aims at achieving the performance of high-end three-dimensional graphics workstations at consumer price points. The TM-PC is a programmable processor with a high-performance, very long instruction word central processing unit (CPU) core. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units), facilitates concurrent processing of audio, video, graphics, and communication data. Designed specifically for the Microsoft Talisman project, TM-PC is a derivative of Philips' TM-1 media processor and is tailored to be used in a variety of PC-based functions as a plug-in board on the peripheral component interconnect (PCI) bus. In the design of the TM-PC, the functionality of most of the blocks from the TM-1 has been kept unchanged; the primary changes in the existing blocks have been in the main memory and the PCI interfaces, and a new block, called VPB, has been added to support virtual frame buffer functionality as well as video graphics adapter and Soundblaster emulation capability. The major emphasis of this paper is on the design details of the new VPB module and an explanation of how it fits with the rest of the TM-1 design.

The programmable video signal processor (VSP) is an important category of processors for multimedia systems. Programmable video processors combine the flexibility of programmability with special architectural features that improve performance on video processing applications. VSPs are typically multiple processors with several processing elements (PEs) and a parallel memory system. This paper focuses on the architectural design of the PE's in a video processor and shows how technology and circuit parameters influence the structure of the datapath and, hence, the overall architecture of a programmable VSP. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture and present a method whereby the conceptual organization of the PEs-the number of PEs, pipelining of the datapath, size of the register file, and number of register ports-can be evaluated in terms of a target set of applications before a detailed design is undertaken. We use motion-estimation and discrete cosine transform as example applications to illustrate how various technology parameters affect the architectural design choices. We show that the design of the register file and the datapath-pipeline depth can drastically affect PE utilization and, therefore, the number of PEs required for different applications. Our results demonstrate that pursuing the fastest cycle time can greatly increase the silicon area which must be devoted to PEs, due to both increased pipeline latency and reduced register file bandwidth.

This paper presents a detailed design study of a high-speed, single-chip architecture for video signal processing (VSP), developed as part of the Princeton VSP Project. In order to define the architectural parameters by examining the area and delay tradeoffs, we start by designing parameterizable versions of key modules, and we perform VLSI modeling experiments in a 0.25 /spl mu/m process. Based on the properties of these modules, we propose a VLIW (very long instruction word) VSP architecture that features 32-64 operations per cycle at clock rates well in excess of 600 MHz, and that includes a significant amount of on-chip memory. VLIW architectures provide predictable, efficient, high performance, and benefit from mature compiler technology. As explained, a VLIW video processor design requires flexible, high-bandwidth interconnect at fast cycle times, and presents some unique VLSI tradeoffs and challenges in maintaining high clock rates while providing high parallelism and utilization.

Develops a methodology for the design of the memory and the memory-processor communication network in video signal processors. The memory subsystem is the bottleneck of most video computing systems and its design requires evaluating tradeoffs between area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly video signal processing (VSP) systems, and present a systematic method whereby the organization of the memory architecture can be analyzed and its cycle-time approximated before a detailed design is undertaken. We show how variations in sizes and circuit configurations help determine the variations in delay of both memory and network, and how the delay curves, thus determined, can be used to design, compare, and choose from different memory-system architectures; we also describe a technique that can be used to identify the on-chip-off-chip boundary with respect to a hierarchical memory-system design for a memory-intensive VSP module. All of our results are validated via layout and simulation of prototype circuits in two different process technologies. Motion estimation and discrete cosine transform (DCT) being two of the most important tasks in video processing, we use the design of a motion estimator and that of a DCT unit as examples to illustrate the high-level issues in designing the memory architecture for a VSP module. The analysis presented for the motion estimator and the DCT unit can also be applied to other processing blocks belonging to the system.

This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellent high-level language programmability, but require careful attention to VLSI and compiler design. Flexible, high-bandwidth interconnect, high-connectivity register files, and fast cycle times are required to achieve real-time video signal processing. Parameterizable versions of key modules have been designed in a 0.25 /spl mu/m process, allowing us to explore tradeoffs in the VLIW VSP design space. The designs target 33 operations per cycle at clock rates exceeding 600 MHz. Various VLIW code scheduling techniques have been applied to 6 VSP kernels and evaluated on 7 different candidate datapath designs. The results of these simulations are used to indicate which architectural tradeoffs enhance overall performance in this application domain.

This paper describes a novel architecture that offers the flexibility of implementing widely varying motion-estimation algorithms. To achieve real-time performance, we employ multiple processing elements (PE's) which communicate with multiple memory banks via a multistage interconnection network. Three different block-matching algorithms-full search, three-step search, and conjugate-direction search-have been mapped onto this architecture to illustrate its programmability. We schedule the desired operations and design the required data-flow in such a way that processor utilization is high and memory bandwidth is at a feasible level. The details regarding the flow of the pixel data and the scheduling and allocation of the desired ALU operations (which pixels are processed on which processors in which clock cycles) are described in the paper. We analyze the performance of the proposed architecture for several different interconnection networks and data-memory organizations.

This paper addresses the design of memory-system architectures for video signal processors. The memory subsystem is the bottleneck of most video computing systems and demands a careful analysis of the design tradeoffs related to area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly that of a video processor, and present a method whereby the conceptual organization of the memory architecture can be evaluated before a detailed design is undertaken. Our analysis suggests that the organization of an efficient memory hierarchy for video signal processors is different from the register-cache based hierarchy of general-purpose programmable microprocessors.

This paper analyzes the effects of technology scaling on video signal processing (VSP) architectures. We evaluate the processor, the memory, and the interconnect delays in terms of sophisticated delay models (that take into account deep-sub-micron device characteristics) and study how the response times of these logic components are affected when the feature sizes scale down. Equations for gate and interconnect delays, as functions of process scaling, are derived and the impact of these results examined in the context of heavily pipelined architectures, architectures featuring crossbar interconnection networks, and architectures whose performance is dominated by memory bandwidth. Architectural parameters such as clock skew, clock frequency, memory interleaving, memory efficiency, and average waiting times are analyzed in the light of the scaling behavior of the gate and the interconnect delays. In the context of scaling of interconnection lines and memory modules, we also highlight how the transmission-line characteristics of long lines are affected by technology scaling and how the delay associated with the memory subsystem-both the memory interleaving and the memory interconnect network-can be a potential bottleneck for the system's speed of operation. It is likely that sophisticated compilation and scheduling techniques must be employed along with architectural optimizations to achieve maximum system performance and ensure that the final hardware-software configuration does not overload the processor-memory communication.

This paper investigates the effects of technology scaling on video signal processing (VSP) architectures. We evaluate the processor, the memory, and the interconnect delays using RC models and study how the response times of these logic components scale with feature size. Architectural parameters such as clock skew, clock frequency, memory interleaving, memory efficiency, and average waiting times are analyzed in the light of the scaling behaviors of the above components.>

This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gate-level functional models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. The optimization technique is based on simulated annealing and considers the performance improvement of VLSI circuits by optimally sizing the transistors on the N most critical paths.>

Considers routability and performance-driven optimization of a segmented channel architecture for row-based field programmable gate arrays (FPGAs). The routability of a channel and the performance of the routed circuit may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. A simulated annealing-based channel segmentation optimization scheme has been developed, which enhances channel routability and performance based on the correlation between segment and net distributions. Excellent results have been obtained for a set of benchmark examples and industrial designs.>

A novel technique is presented for analyzing nonlinear active devices driving RC trees which accounts for nonlinear behavior in such a way that the accuracy obtained is typically within 10% of SPICE. This is achieved with a tremendous savings in calculation time as compared to SPICE, using exclusively DC parameterized transistor models. These models have been included in a prototype program for analyzing bipolar and CMOS logic-stage delay models. These techniques are currently being extended to provide best-case and worst-case delay approximations in terms of the DC parameterized piecewise-linear and piecewise-quadratic Thevenin models.>

A simple but accurate delay model is presented for both simple and complex static logic gates. Unlike the previous delay models which assume the worst-case scenario, the present model has the capability of handling the different input switching conditions. In the delay analysis of a circuit, failing to take into account the position of the transistor that is switching can result in a delay value which is off by a margin of 100% or more from the actual. This novel modeling technique has been implemented in LISP on a TI Explorer II workstation Lisp Machine as a part of the DROID design automation environment.>