Maintaining a scalable high-performance virtual global address space using distributed memory hardware has proven to be challenging. In this paper we evaluate a new approach for such an active global address space that leverages the capabilities of the network fabric to manage addressing, rather than software at the endpoint hosts. We describe our overall approach, design alternatives, and present initial experimental results that demonstrate the effectiveness and limitations of existing network hardware.

This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. In this paper, we present the progress of our research on a parallel programming and execution model - mainly, ParalleX. We describe the functional elements of ParalleX, one such model being explored as part of this project. We also report our progress on the development and study of a subset of ParalleX $the LITL-X at University of Delaware. We then present a novel architecture model - Gilgamesh II - as a ParalleX processing architecture. A design point study of Gilgamesh II and the architecture concept strategy are presented.

Summary form only given. Heterogeneous system architecture has long been appreciated as a potential strategy for achieving super-linear speedup with respect to some normalizing parameter like number of nodes, cost, or power. However the challenge of programming and managing the system resources has been a limiting factor for the application of such systems on a broad scale. The exception has been the use of special purpose processors such as graphics processing units that may yield dramatic increases for such functionality enabling capabilities largely impossible otherwise like realistic high resolution real time interactive games. However, with power emerging as the dominant constraint on high performance computing and the need to make better use of logic and storage resources such components as the ClearSpeed SIMD attached processor and the IBM cell architectures among others is forcing mainstream computing to adopt heterogeneous processing. This keynote presentation describes a computational model, ParalleX that provides an asynchronous runtime framework for supporting effective execution in an environment comprising heterogeneous elements. ParalleX is based on a message-driven split-phase multithreaded transaction processing paradigm synthesizing a number of concepts represented in prior art that in ensemble facilitates management of heterogeneous resources and provides the basis for a systematic programming methodology. Also discussed in this presentation is another example of a heterogeneous architecture, Gilgamesh II, that provides separate mechanisms for computations that exhibit disparate locality properties.

This paper addresses the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and the difficulties of programmer productivity (e.g. explicit locality management and scheduling, performance tuning, fragmented memory, and synchronous global barriers) to dramatically enhance the broad effectiveness of parallel processing for high end computing. We are developing a hierarchical threaded virtual machine (HTVM) that defines a dynamic, multithreaded execution model and programming model, providing an architecture abstraction for HEC system software and tools development. We are working on a prototype language, LITL-X (pronounced "little-X") for latency intrinsic-tolerant language, which provides the application programmers with a powerful set of semantic constructs to organize parallel computations in a way that hides/manages latency and limits the effects of overhead. This is quite different from locality management, although the intent of both strategies is to minimize the effect of latency on the efficiency of computation. We work on a dynamic compilation and runtime model to achieve efficient LITL-X program execution. Several adaptive optimizations were studied. A methodology of incorporating domain-specific knowledge in program optimization was studied. Finally, we plan to implement our method in an experimental testbed for a HEC architecture and perform a qualitative and quantitative evaluation on selected applications

Experts in advanced system technologies will predict the design of the best HPC architectures in 2020. They will defend why they think the technology they select will be the winning technology 15 years from now. The panelists will pick one set of technology - not a list of possibilities - to define the system. They will define the performance and aspects of the technologies and explain why their system is the most likely to succeed.Besides questions and comments at the sessions, attendees will vote for the proposed systems of 2020 they think are most likely to succeed. The presentations, votes and attendee comments will all be sealed in a time capsule that will be opened in 2020, which will be used in 2020 to compare the predications to reality. The time capsule will also include an appropriate prize for the presenter who made the best prediction. The winner needs to be present to collect their prize.

Twenty five years ago supercomputing was dominated by vector processors and emergent SIMD array processors clocked at tens of Megahertz. Today responding to dramatic advances in semiconductor device fabrication technologies, the world of supercomputing is dominated by multi-core based MPP and commodity cluster systems clocked at Gigahertz. Twenty five years in the future, the technology landscape will again have experienced dramatic change with the flat-lining of Moore's Law, the realization of nanoscale devices, and the emergence of potentially alien technologies, architectures, and paradigms. If Moore's Law were to continue to progress as before, we would be deploying systems approaching 100 Exaflops with clock rates nearing a Terahertz. But by then, power constraints, quantum effects, or our inability to exploit trillion way program parallelism may have forced us in to entirely new realms of processing. This presentation will consider the range of alternative technologies, architectures, and methods that may drive the extremes of computing beyond the current incremental steps of the current era.

A dramatic trend in computing is the adoption of multi-core technology by the vendors from which our current and future HPC systems are being derived. Multi-core is offered as a path to continued reliance and benefits of Moore's Law while reining in the previously unfettered growth of power consumption and design complexity. Are we saved? or is it but a fools mission, trapping us in a technical cul de sac with no long term direction and no way to reinvent an alternative future. The panel will consider the following questions:* Can multi-core span the next decade of Moore's Law progression?* Are the pins and caches a strangle hold on the future effectiveness of multi-core?* Can innovative algorithmic techniques exploit the opportunities and address the challenges of multi-core?* How will programming models and supporting system software change to accommodate the unique properties and peculiarities of multi-core structures?

The challenges to extending the delivered computing capabilities of semiconductor technology through Moore?s Law, while manageable in the short term, may prove difficult or possibly impractical in the long term. Even now, the complex interplay of power and performance is resulting in significant changes in previous trends. Clock rates of commodity microprocessors are flattening even as multi-core chips are emerging as the norm for next generation systems. While conventional wisdom has dictated an assumption of continued adherence to the pure CMOS tradition of the last decade and more, the supercomputing community must consider the possibility of alternative technologies, at least in combination with more conventional devices. More than just changing or augmenting the technology base, new architecture structures and programming models may need to be considered and multiple levels to exploit the potential of such advances. This panel addresses these issues with a focus on one possible alternative technology: superconductor devices. Rapid Single Flux Quantum (RSFQ) logic exhibits operational properties in terms of performance and power that now positions it as a potential future leader among alternative digital technologies to augment semiconductor components in hybrid systems. But it is also challenged by lack of maturity and commercial market as well as its reliance on extreme operational temperature regimes. This panel brings together leaders in the fields of technology and computer architecture to consider the possible strategies and potential viability of superconductor based supercomputing.

A major trend in high performance computer architecture over the last two decades is the migration of memory in the form of high speed caches onto the microprocessor semiconductor die. Where temporal locality in the computation is high, caches prove very effective at hiding memory access latency and contention for communication resources. However where temporal locality is absent, caches may exhibit low hit rates resulting in poor operational efficiency. Vector computing exploiting pipelined arithmetic units and memory access address this challenge for certain forms of data access patterns, for example involving long contiguous data sets exhibiting high spatial locality. But for many advanced applications for science, technology, and national security at least some data access patterns are not consistent to the restricted forms well handled by either caches or vector processing. An important alternative is the reverse strategy; that of migrating logic in to the main memory (DRAM) and performing those operations directly on the data stored there. Processor in Memory (PIM) architecture has advanced to the point where it may fill this role and provide an important new mechanism for improving performance and efficiency of future supercomputers for a broad range of applications. One important project considering both the role of PIM in supercomputer architecture and the design of such PIM components is the Cray Cascade Project sponsored by the DARPA High Productivity Computing Program. Cascade is a Petaflops scale computer targeted for deployment at the end of the decade that merges the raw speed of an advanced custom vector architecture with the high memory bandwidth processing delivered by an innovative class of PIM architecture. The work represented here was performed under the Cascade project to explore critical design space issues that will determine the value of PIM in supercomputers and contribute to the optimization of its design. But this work also has strong relevance to hybrid systems comprising a combination of conventional microprocessors and advanced PIM based intelligent main memory.

Summary form only given. It is observed that once you've finally made it to the North Pole, no matter what direction your next step takes, you can't go anywhere but South. To some, it appears that Commodity Cluster computing is in somewhat of a similar position. Having firmly established itself as the leading approach to scalable high performance computing, commodity clusters such as Beowulf-class systems have no where to go. Yes, they will continue to track Moore's exponential growth in peak performance and storage capacity, and system software will become incrementally better But in terms of strategic advances, commodity clusters are largely corralled in a paradigm cul-de-sac. In some sense there is a kind of truth in this assessment: the fundamental premise of commodity clustering is invariant; Existing, i.e. predeveloped and standalone, systems (uninformatively referred to as "nodes") are integrated by means of a commercially available interconnect network and supporting software. However the flaw of this defeatist perspective is that the nodes look like more of the same, only faster The future of commodity cluster computing will be defined, not solely by Moore's Law, but by the revolutionary structures embodied by the nodes and the innovative ways in which they will be employed. This plenary presentation will explore the innovations in both hardware and software that are likely to drive the future of commodity cluster computing throughout the rest of this decade and toward the trans-Petaflops performance regime of performance. In so doing, we will examine current projections of device technology to anticipate the performance, capacity, power, size, and cost curves of future commodity clusters. Perhaps of more impact are the changes anticipated in hardware architecture including blade technology, system and SMP on a chip, processor in memory architecture, and anticipated advances in networking including Infiniband and optical switching. As new uses are found for clusters with a rapidly expanding customer base including commercial and business communities, a combination of open source and commercial software tools will be developed for ease of use and high productivity as well as resource management and fault recovery As system scale explodes even for moderate cost systems, the software tools to manage them will take on new responsibilities alleviating much of the burden experienced by today's practitioners. The talk will conclude with a look at some more bizarre possibilities made driven by other market and product trends. The future of clusters can show that even at the North Pole, with the right technology and vision, you can also go straight up.

Processor-in-Memory (PIM) architectures avoid the von Neumann bottleneck in conventional machines by integrating high-density DRAM and CMOS logic on the same chip. Parallel systems based on this new technology are expected to provide higher scalability, adaptability, robustness, fault tolerance and lower power consumption than current MPPs or commodity clusters. In this paper we describe the design of Gilgamesh a PIM-based massively parallel architecture, and elements of its execution model. Gilgamesh extends existing PIM capabilities by incorporating advanced mechanisms for virtualizing tasks and data and providing adaptive resource management for load balancing and latency tolerance. The Gilgamesh execution model is based on macroservers a middleware layer which supports object-based runtime management of data and threads allowing explicit and dynamic control of locality and load balancing. The paper concludes with a discussion of related research activities and an outlook to future work.

Article Microservers: a new memory semantics for massively parallel computing Share on Authors: Jay B. Brockman Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, INView Profile , Peter M. Kogge Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, INView Profile , Thomas L. Sterling Center for Advanced Computing Research, California Institute of Technology, Pasadena, CA Center for Advanced Computing Research, California Institute of Technology, Pasadena, CAView Profile , Vincent W. Freeh Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, INView Profile , Shannon K. Kuntz Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, INView Profile Authors Info & Claims ICS '99: Proceedings of the 13th international conference on SupercomputingJune 1999 Pages 454–463https://doi.org/10.1145/305138.305234Online:01 May 1999Publication History 29citation567DownloadsMetricsTotal Citations29Total Downloads567Last 12 Months9Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The future of Beowulf-class PC clusters for large-scale scientific and engineering applications will be determined by three issues: system scalability; latency tolerant applications development; and software environments and tools. This paper focuses on the first of these, scalability, which is sensitive to aspects of the remaining two. For the studies and findings described, we consider system designs capable of integrating hundreds or thousands of processors.

Beowulf-class systems employ inexpensive commodity processors, open source operating systems and communication libraries and commodity networking hardware to deliver supercomputer performance at the lowest possible price. Small to medium sized Beowulf systems are installed or planned at dozens of universities, laboratories and industrial sites around the world. The design space for larger systems, however, is largely unexplored. We investigate two interconnection techniques that would allow the scaling of a Beowulf class system to unprecedented sizes (hundreds or thousands of processors). The first is a commercially available high-speed backplane with fast-ethernet and gigabit ethernet switch modules. The second is a network that combines point- to-point connections and commodity switches, employing the Beowulf nodes as IP routers as well as computational engines. The first method has the drawback of a relatively high price tag - a significant but not overwhelming fraction of the cost of the system must be devoted to the switch. The second approach is inexpensive, but introduces extra latency and may restrict bandwidth depending on the topology employed. Our tests are designed to quantify these effects. We perform three sets of tests. Low-level tests measure the hardware performance of the individual components, i.e., bandwidths and latencies through various combinations of network interface cards, node- based routers and switches. System-level tests measure the bisection bandwidth and the ability of the system to communicate and compute simultaneously, under conditions designed to generate contention and heavy loads. Finally, application benchmarks measure the performance delivered to a subset of the NAS parallel benchmark suite. Low-level measurements indicate that latencies are only weakly affected by introduction of node-based routers, and that bandwidths are completely unaffected. Switches introduce between 19 and 30 microseconds of latency and linux-based routers introduce 75 microseconds. System level measurements indicate that even under load, the routed network delivers a bisection bandwidth near what one would expect by simply summing the capacities of the individual components. A very large scatter is introduced into latencies, however. Application level measurements reveal that the routed network is acceptable for some applications, but can have significant deleterious effect on others. Successful use of routed networks for very large beowulf systems will requires a deeper understanding of this issue.

Coupling PC based commodity technology with distributed computing methodologies provides on important advance in the development of single user dedicated systems. Beowulf is a class of experimental parallel workstations developed to evaluate and characterize the design space of this new operating point in price performance. A key factor determining the realizable performance under real world workloads is the means devised for interprocessor communications. A study has been performed to characterize a family of interconnect topologies feasible with low cost mass market network technologies. Behavior sensitivities to packet size and traffic density are determined. Findings are presented which compare more complex segmented topologies to the earlier parallel "channel bonded" scheme. It is shown that in many circumstances the more complex topologies perform better, and in some circumstances software routing techniques compare favorably to more expensive hardware switch mechanisms.

The Convex SPP-1000, the most recent SPC, is distinguished by a true global shared memory capability based on the first commercial version of directory based cache coherence mechanisms and SCI protocol. The system was evaluated at NASA/GSFC in the Beta-test environment using three classes of operational experiments targeting earth and space science applications. A multiple program workload tested job-stream level parallelism. Synthetic programs measured overhead costs of barrier, fork-join, and message passing synchronization primitives. An efficient tree-code version of an N-body simulation revealed scaling properties and measured the overall efficiency. This paper presents the results of this study and provides the earliest published evaluation of this new scalable architecture.>

The Beowulf parallel workstation combines 16 PC-compatible processing subsystems and disk drives using dual Ethernet networks to provide a single-user environment with 1 Gops peak performance, half a Gbyte of disk storage, and up to 8 times the disk I/O bandwidth of conventional workstations. The Beowulf architecture establishes a new operating point in price-performance for single-user environments requiring high disk capacity and bandwidth. The Beowulf research project is investigating the feasibility of exploiting mass market commodity computing elements in support of Earth and space science requirements for large data-set browsing and visualization, simulation of natural physical processes, and assimilation of remote sensing data. This paper reports the findings from a series of experiments for characterizing the Beowulf dual channel communication over-head. It is shown that dual networks can sustain 70% greater throughput than a single network alone but that bandwidth achieved is more highly sensitive to message size than to the number of messages at peak demand. While overhead is shown to be high for global synchronization, its overall impact on scalability of real world applications for computational fluid dynamics and N-body gravitational simulation is shown to be modest.

No abstract available.

The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical structure of processing communication and memory name-space management resources to provide a scalable NUMA environment. Ensembles of 8 HPPA-RISC7100 microprocessorsemploy an internal cross-bar switch and directory based cache coherence scheme to provide a tightly coupled SMP.Up to 16 processing ensembles are interconnected by a 4 ring network incorporating a full hardware implementation of the SCI protocol for a full system configuration of 128 processors. This paper presents the findings of a set of empirical studies using both synthetic test codes and full applications for the Earth and space sciences to characterize the performance properties of this new architecture. It is shown that overhead and latencies of global primitive mechanisms, while low in absolute time, are significantly more costl...

The static data-flow model of computation promises high-performance from fine-grained parallelism, but conventional token-driven static data-flow architectures are inefficient in terms of memory bandwidth and microcycles required per operation. The associative template mechanism, an application of associative techniques, uses specially configured content-addressable memories to provide efficient flow control for static data-flow program execution. It supports static data-flow semantics while exhibiting memory bandwidth and microcycle demands comparable to those of conventional uniprocessors. Associative diffusion, a second application of associative methods, provides a communication between adjacent nodes of a mesh-connected network of associative-template-based processors. This mechanism achieves nearest-neighbor communication at speeds comparable to intranode transactions by overlapping domains of associativity across boundaries between neighboring nodes. Together, associative templates and associative diffusion provide a token-free approach to static data-flow computation.>

Concert is a shared-memory multiprocessor testbed intended to facilitate experimentation with parallel programs and programming languages. It consists of up to eight clusters, with 4-8 processors in each cluster. The processors in each cluster communicate using a shared bus, but each processor also has a private path to some memory. The novel feature of Concert is the RingBus , a segmented bus in the shape of a ring that permits communication between clusters at relatively low cost. Efficient arbitration among requests to use the RingBus is a major challenge, which is met by a novel hardware organization, the criss-cross arbiter . Simulation of the Concert RingBus and arbiter show their performance to lie between that of a crossbar switch and a simple shared intercluster bus.